From mboxrd@z Thu Jan 1 00:00:00 1970 From: Manish Narani Subject: [PATCH v5 4/4] arm64: zynqmp: Add DDRC node Date: Fri, 31 Aug 2018 18:57:50 +0530 Message-ID: <1535722070-10394-5-git-send-email-manish.narani@xilinx.com> References: <1535722070-10394-1-git-send-email-manish.narani@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1535722070-10394-1-git-send-email-manish.narani@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org To: robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com, bp@alien8.de, mchehab@kernel.org, manish.narani@xilinx.com, leoyang.li@nxp.com, amit.kucheria@linaro.org, olof@lixom.net Cc: sgoud@xilinx.com, anirudh@xilinx.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org List-Id: devicetree@vger.kernel.org Add ddrc memory controller node in dts. The size mentioned in dts is 0x30000, because we need to access DDR_QOS INTR registers located at 0xFD090208 from this driver. Signed-off-by: Manish Narani --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 29ce234..a81d3b16 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -355,6 +355,13 @@ xlnx,bus-width = <64>; }; + mc: memory-controller@fd070000 { + compatible = "xlnx,zynqmp-ddrc-2.40a"; + reg = <0x0 0xfd070000 0x0 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 112 4>; + }; + gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; -- 2.1.1