From: Alan Douglas <adouglas@cadence.com>
To: kishon@ti.com, linux-kernel@vger.kernel.org,
mark.rutland@arm.com, robh+dt@kernel.org,
devicetree@vger.kernel.org
Cc: Alan Douglas <adouglas@cadence.com>
Subject: [RFC PATCH v2 0/2] phy: cadence: Add driver and dt-bindings for Sierra PHY
Date: Thu, 6 Sep 2018 15:41:10 +0100 [thread overview]
Message-ID: <1536244870-23149-1-git-send-email-adouglas@cadence.com> (raw)
The Cadence Sierra PHY supports a number of different protocols. This
series adds a driver with support for USB3 and PCIe modes.
Only one clock frequency is currently supported, so the value of clock
provided in device tree is ignored.
Changes from v1:
* Each group of lanes is now treated as a subnode, and a generic PHY
device is created for each group.
* General cleanup based on comments
* A reset is now required for each subnode. The complete PHY block
is taken out of reset at initial probe, and remains out of reset.
* Added a binding to allow for hardware configuration of PHY registers
Alan Douglas (2):
dt-bindings: phy: Document cadence Sierra PHY bindings
phy: cadence: Add driver for Sierra PHY
.../devicetree/bindings/phy/cdns-sierra-phy.txt | 65 ++++
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/cadence/Kconfig | 9 +
drivers/phy/cadence/Makefile | 2 +
drivers/phy/cadence/cdns-sierra.c | 385 +++++++++++++++++++++
6 files changed, 463 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/cdns-sierra-phy.txt
create mode 100644 drivers/phy/cadence/Kconfig
create mode 100644 drivers/phy/cadence/Makefile
create mode 100644 drivers/phy/cadence/cdns-sierra.c
--
1.9.0
reply other threads:[~2018-09-06 14:41 UTC|newest]
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