[PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device

[PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device

[Jim Quinlan]

The DT bindings description of the Brcmstb PCIe device is described.
This node can be used by almost all Broadcom settop box chips, using
ARM, ARM64, or MIPS CPU architectures.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/brcmstb-pcie.txt       | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
new file mode 100644
index 0000000..a1a9ad5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
@@ -0,0 +1,59 @@
+Brcmstb PCIe Host Controller Device Tree Bindings
+
+Required Properties:
+- compatible
+  "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
+  "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
+  "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
+      the 7278).
+  "brcm,bcm7278-pcie"  -- for 7278 family ARM-based SOCs.
+
+- reg -- the register start address and length for the PCIe reg block.
+- interrupts -- two interrupts are specified; the first interrupt is for
+     the PCI host controller and the second is for MSI if the built-in
+     MSI controller is to be used.
+- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
+- #address-cells -- set to <3>.
+- #size-cells -- set to <2>.
+- #interrupt-cells: set to <1>.
+- interrupt-map-mask and interrupt-map, standard PCI properties to define the
+     mapping of the PCIe interface to interrupt numbers.
+- ranges: ranges for the PCI memory and I/O regions.
+- linux,pci-domain -- should be unique per host controller.
+
+Optional Properties:
+- clocks -- phandle of pcie clock.
+- clock-names -- set to "sw_pcie" if clocks is used.
+- dma-ranges -- Specifies the inbound memory mapping regions when
+     an "identity map" is not possible.
+- msi-controller -- this property is typically specified to have the
+     PCIe controller use its internal MSI controller.
+- msi-parent -- set to use an external MSI interrupt controller.
+- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking.
+- max-link-speed --  (integer) indicates desired generation of link:
+     1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
+
+Example Node:
+
+pcie0: pcie@f0460000 {
+		reg = <0x0 0xf0460000 0x0 0x9310>;
+		interrupts = <0x0 0x0 0x4>;
+		compatible = "brcm,bcm7445-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
+			  0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &intc 0 47 3
+				 0 0 0 2 &intc 0 48 3
+				 0 0 0 3 &intc 0 49 3
+				 0 0 0 4 &intc 0 50 3>;
+		clocks = <&sw_pcie0>;
+		clock-names = "sw_pcie";
+		msi-parent = <&pcie0>;  /* use PCIe's internal MSI controller */
+		msi-controller;         /* use PCIe's internal MSI controller */
+		brcm,ssc;
+		max-link-speed = <1>;
+		linux,pci-domain = <0>;
+	};
-- 
1.9.0.138.g2de3478

Re: [PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device

[Jonas Gorski]

On 19 September 2018 at 16:31, Jim Quinlan <jim2101024@gmail.com> wrote:
> The DT bindings description of the Brcmstb PCIe device is described.
> This node can be used by almost all Broadcom settop box chips, using
> ARM, ARM64, or MIPS CPU architectures.

Oh, hey, *one* email made it finally through :P

>
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/pci/brcmstb-pcie.txt       | 59 ++++++++++++++++++++++
>  1 file changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
> new file mode 100644
> index 0000000..a1a9ad5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
> @@ -0,0 +1,59 @@
> +Brcmstb PCIe Host Controller Device Tree Bindings
> +
> +Required Properties:
> +- compatible
> +  "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
> +  "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
> +  "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
> +      the 7278).
> +  "brcm,bcm7278-pcie"  -- for 7278 family ARM-based SOCs.
> +
> +- reg -- the register start address and length for the PCIe reg block.
> +- interrupts -- two interrupts are specified; the first interrupt is for
> +     the PCI host controller and the second is for MSI if the built-in
> +     MSI controller is to be used.
> +- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
> +- #address-cells -- set to <3>.
> +- #size-cells -- set to <2>.
> +- #interrupt-cells: set to <1>.
> +- interrupt-map-mask and interrupt-map, standard PCI properties to define the
> +     mapping of the PCIe interface to interrupt numbers.
> +- ranges: ranges for the PCI memory and I/O regions.
> +- linux,pci-domain -- should be unique per host controller.
> +
> +Optional Properties:
> +- clocks -- phandle of pcie clock.
> +- clock-names -- set to "sw_pcie" if clocks is used.
> +- dma-ranges -- Specifies the inbound memory mapping regions when
> +     an "identity map" is not possible.
> +- msi-controller -- this property is typically specified to have the
> +     PCIe controller use its internal MSI controller.
> +- msi-parent -- set to use an external MSI interrupt controller.
> +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking.
> +- max-link-speed --  (integer) indicates desired generation of link:
> +     1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
> +
> +Example Node:
> +
> +pcie0: pcie@f0460000 {
> +               reg = <0x0 0xf0460000 0x0 0x9310>;
> +               interrupts = <0x0 0x0 0x4>;

Your binding says two interrupts, your example has three - what's the
third interrupt for? Also you define the same for MSI and PCIe (I
assume) - is that expected? Are there systems where they are
different? I would expect the msi interrupt to be optional for the
case where its the same as the pcie one, and only required if it is
different.

Also your binding requires an interrupt-names propery, but it's
missing from the example.

> +               compatible = "brcm,bcm7445-pcie";
> +               #address-cells = <3>;
> +               #size-cells = <2>;
> +               ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
> +                         0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
> +               #interrupt-cells = <1>;
> +               interrupt-map-mask = <0 0 0 7>;
> +               interrupt-map = <0 0 0 1 &intc 0 47 3
> +                                0 0 0 2 &intc 0 48 3
> +                                0 0 0 3 &intc 0 49 3
> +                                0 0 0 4 &intc 0 50 3>;
> +               clocks = <&sw_pcie0>;
> +               clock-names = "sw_pcie";
> +               msi-parent = <&pcie0>;  /* use PCIe's internal MSI controller */
> +               msi-controller;         /* use PCIe's internal MSI controller */
> +               brcm,ssc;
> +               max-link-speed = <1>;
> +               linux,pci-domain = <0>;
> +       };
> --
> 1.9.0.138.g2de3478
>

Regards
Jonas

Re: [PATCH v5 02/12] dt-bindings: pci: add DT docs for Brcmstb PCIe device

[Jim Quinlan]

On Thu, Sep 20, 2018 at 5:06 AM Jonas Gorski <jonas.gorski@gmail.com> wrote:
>
> On 19 September 2018 at 16:31, Jim Quinlan <jim2101024@gmail.com> wrote:
> > The DT bindings description of the Brcmstb PCIe device is described.
> > This node can be used by almost all Broadcom settop box chips, using
> > ARM, ARM64, or MIPS CPU architectures.
>
> Oh, hey, *one* email made it finally through :P

Sigh, I'm still having email issues, my apologies.

>
> >
> > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
> >  .../devicetree/bindings/pci/brcmstb-pcie.txt       | 59 ++++++++++++++++++++++
> >  1 file changed, 59 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
> > new file mode 100644
> > index 0000000..a1a9ad5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
> > @@ -0,0 +1,59 @@
> > +Brcmstb PCIe Host Controller Device Tree Bindings
> > +
> > +Required Properties:
> > +- compatible
> > +  "brcm,bcm7425-pcie" -- for 7425 family MIPS-based SOCs.
> > +  "brcm,bcm7435-pcie" -- for 7435 family MIPS-based SOCs.
> > +  "brcm,bcm7445-pcie" -- for 7445 and later ARM based SOCs (not including
> > +      the 7278).
> > +  "brcm,bcm7278-pcie"  -- for 7278 family ARM-based SOCs.
> > +
> > +- reg -- the register start address and length for the PCIe reg block.
> > +- interrupts -- two interrupts are specified; the first interrupt is for
> > +     the PCI host controller and the second is for MSI if the built-in
> > +     MSI controller is to be used.
> > +- interrupt-names -- names of the interrupts (above): "pcie" and "msi".
> > +- #address-cells -- set to <3>.
> > +- #size-cells -- set to <2>.
> > +- #interrupt-cells: set to <1>.
> > +- interrupt-map-mask and interrupt-map, standard PCI properties to define the
> > +     mapping of the PCIe interface to interrupt numbers.
> > +- ranges: ranges for the PCI memory and I/O regions.
> > +- linux,pci-domain -- should be unique per host controller.
> > +
> > +Optional Properties:
> > +- clocks -- phandle of pcie clock.
> > +- clock-names -- set to "sw_pcie" if clocks is used.
> > +- dma-ranges -- Specifies the inbound memory mapping regions when
> > +     an "identity map" is not possible.
> > +- msi-controller -- this property is typically specified to have the
> > +     PCIe controller use its internal MSI controller.
> > +- msi-parent -- set to use an external MSI interrupt controller.
> > +- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking.
> > +- max-link-speed --  (integer) indicates desired generation of link:
> > +     1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).
> > +
> > +Example Node:
> > +
> > +pcie0: pcie@f0460000 {
> > +               reg = <0x0 0xf0460000 0x0 0x9310>;
> > +               interrupts = <0x0 0x0 0x4>;
>
> Your binding says two interrupts, your example has three - what's the
> third interrupt for?

Actually that's a single interrupt with three cells.  I need to add
another interrupt.  Note that we have #interrupt-cells set to 1
because that is for the legacy interrupts given in the interrupt-map.

> Also you define the same for MSI and PCIe (I assume) - is that expected?
No, these will be updated to two different interrupts.

Are there systems where they are
> different? I would expect the msi interrupt to be optional for the
> case where its the same as the pcie one, and only required if it is
> different.
>
> Also your binding requires an interrupt-names propery, but it's
> missing from the example.
Will fix.

Thanks,
Jim
>
> > +               compatible = "brcm,bcm7445-pcie";
> > +               #address-cells = <3>;
> > +               #size-cells = <2>;
> > +               ranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000
> > +                         0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;
> > +               #interrupt-cells = <1>;
> > +               interrupt-map-mask = <0 0 0 7>;
> > +               interrupt-map = <0 0 0 1 &intc 0 47 3
> > +                                0 0 0 2 &intc 0 48 3
> > +                                0 0 0 3 &intc 0 49 3
> > +                                0 0 0 4 &intc 0 50 3>;
> > +               clocks = <&sw_pcie0>;
> > +               clock-names = "sw_pcie";
> > +               msi-parent = <&pcie0>;  /* use PCIe's internal MSI controller */
> > +               msi-controller;         /* use PCIe's internal MSI controller */
> > +               brcm,ssc;
> > +               max-link-speed = <1>;
> > +               linux,pci-domain = <0>;
> > +       };
> > --
> > 1.9.0.138.g2de3478
> >
>
> Regards
> Jonas

[PATCH v5 08/12] MIPS: BMIPS: add PCI bindings for 7425, 7435

[Jim Quinlan]

Adds the PCIe nodes for the Broadcom STB PCIe root complex.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7425.dtsi     | 28 ++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm7435.dtsi     | 28 ++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97425svmb.dts |  4 ++++
 arch/mips/boot/dts/brcm/bcm97435svmb.dts |  4 ++++
 4 files changed, 64 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index 410e61e..0edcbe4 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -584,4 +584,32 @@
 			};
 		};
 	};
+
+	pcie: pcie@10410000 {
+		reg = <0x10410000 0x830c>;
+		compatible = "brcm,bcm7425-pcie";
+		interrupts = <37>, <37>;
+		interrupt-names = "pcie", "msi";
+		interrupt-parent = <&periph_intc>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		linux,pci-domain = <0>;
+		brcm,enable-ssc;
+		bus-range = <0x00 0xff>;
+		msi-controller;
+		#interrupt-cells = <1>;
+		/* 4x128mb windows */
+		ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0x0 0x20000000>;
+		/* 768M or 1GB memc0, 0-1GB memc1 */
+		dma-ranges =
+			<0x02000000 0x0 0x00000000 0x00000000 0x0 0x10000000>,
+			<0x02000000 0x0 0x10000000 0x20000000 0x0 0x30000000>,
+			<0x02000000 0x0 0x40000000 0x90000000 0x0 0x40000000>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &periph_intc 33
+				 0 0 0 2 &periph_intc 34
+				 0 0 0 3 &periph_intc 35
+				 0 0 0 4 &periph_intc 36>;
+	};
+
 };
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 8398b7f..50bc7a0 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -599,4 +599,32 @@
 			};
 		};
 	};
+
+	pcie: pcie@10410000 {
+		reg = <0x10410000 0x930c>;
+		interrupts = <0x27>, <0x27>;
+		interrupt-names = "pcie", "msi";
+		interrupt-parent = <&periph_intc>;
+		compatible = "brcm,bcm7435-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		linux,pci-domain = <0>;
+		brcm,enable-ssc;
+		bus-range = <0x00 0xff>;
+		msi-controller;
+		#interrupt-cells = <1>;
+		ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0x0 0x20000000>;
+		/* 768M or 1GB memc0, 0-1GB memc1 */
+		dma-ranges =
+			<0x02000000 0x0 0x00000000 0x00000000 0x0 0x10000000>,
+			<0x02000000 0x0 0x10000000 0x20000000 0x0 0x30000000>,
+			<0x02000000 0x0 0x40000000 0x90000000 0x0 0x40000000>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &periph_intc 35
+				 0 0 0 2 &periph_intc 36
+				 0 0 0 3 &periph_intc 37
+				 0 0 0 4 &periph_intc 38>;
+		status = "disabled";
+	};
+
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index 0ed2221..22270a9 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -152,3 +152,7 @@
 &waketimer {
 	status = "okay";
 };
+
+&pcie {
+	status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index 2c145a8..91bc1ec 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -128,3 +128,7 @@
 &waketimer {
 	status = "okay";
 };
+
+&pcie {
+	status = "okay";
+};
-- 
1.9.0.138.g2de3478

[PATCH v5 00/12] PCI: brcmstb: Add Broadcom Settopbox PCIe support

[Jim Quinlan]

This patch series adds support for the Broadcom Settopbox PCIe host
controller.  It is targeted to Broadcom Settopbox chips running on
ARM, ARM64, and MIPS platforms.

V5 Changes:
  - V4 had its own DMA ops structure in the PCIe driver which would
    override/coexist with the default arch DMA ops.  This approach was
    scrapped, and this version instead essentially implements custom
    definitions of the __phys_to_dma and __dma_to_phys operations for the
    three target arches: MIPs, ARM64, ARM.  This was the course suggested
    by one of the V4 reviewers (ChristophH).

    For MIPs and ARM64, the DMA remapping is easily accomplished by having
    custom definitions of __phys_to_dma and __dma_to_phys.  For
    MIPs/BMIPs, ARCH_HAS_PHYS_TO_DMA is already selected and the two
    functions are just modified.  For ARM64, this driver selects
    ARCH_HAS_PHYS_TO_DMA and declares and defines __phys_to_dma() and
    __dma_to_phys().  For ARM, things were not so simple.  The default
    functions like __arch_pfn_to_dma() had to be overridden by custom ones
    defined in arch/arm/mach-bcm/include/mach/memory.h.  For these
    functions to be "seen", we had to declare our own brcmstb_defconfig
    and no longer use multi_v7_defconfig.  This is unfortunate.

  - Commits have been better organized to first implement the main driver,
    then add features (MSI, DMA remap infrastructure), and then add
    the DMA remapping modifications for MIPs, ARM64, and ARM.

V4 Changes:
  - Merged all BrcmSTB PCIe controller files into a single file.
  - All new files now have the SPDX identifier.
  - Removed the list of PCIe controllers.
  - Removed "link-up" race.
  - Removed probe of msi psuedo-device.
  - Multiple comment text changes, as requested.
  - "SSC" => "Spread Spectrum Clocking".
  - Set 'memc' variable.
  - Unnecessary variable initializations removed (eg rc_bar2_size).
  - Added comment on "L23" link state.
  - Removed use of "__refdata".
  - Formatting of structure elements.

V3 Changes:
  - Fold pcie-brcmstb-msi.c into pcie-brcmstb.c
  - Use PCI_XXX constants for PCIe capability registers
  - Removal of any unused constants
  - Change s/pci/pcie/ for filenames, comment text
  - Config space access now uses 8/16/32 read/writes
  - Use proper multi-line comment style
  - Use function names, structure that are common in other host drivers
  - DT binding 'brcm,ssc' is now 'brcm,enable-ssc'
  - Dropped DT binding 'xyz-supply'
  - Not setting CRS support as Linux does it if it is advertised.
  - Removed code that was considered "debug code".
  - Use of_get_pcie_domain_nr()
  - Variable 'bridge_setup_done' removed.

V2 Changes:
* Patch brcmstb-add-memory-API:
  - fix DT_PROP_DATA_TO_U32 macro.
  - dropped one EXPORT_SYMBOL, changed the other to GPL.
* Patch DT-docs-for-Brcmstb-PCIe:
  - change 'brcm,gen' prop to standard 'max-link-speed'.
  - rewrite bindings commit to omit standard prop defs.
  - change props "supplies", "supply-names" to "xyz-supply"
* Patch removed: export-symbol-arch_setup_dma_ops [4/9]
* Patch brcmstb-add-dma-ranges:
  - use get_dma_ops(); also use a const dma_map_ops structure.
  - rewrite map_sg(), unmap_sg(), other calls like syng_sg_*()
  - omit brcm_mapping_error(), but added code in brcm_dma_supported()
  - put all of the notifier code in one compilation unit.



Florian Fainelli (1):
  soc: bcm: brcmstb: add memory API

Jim Quinlan (11):
  dt-bindings: pci: add DT docs for Brcmstb PCIe device
  PCI: brcmstb: add Broadcom STB PCIe host controller driver
  PCI: brcmstb: add dma-range mapping for inbound traffic
  PCI: brcmstb: add MSI capability
  MIPS: BMIPS: add dma remap for BrcmSTB PCIe
  PCI/MSI: enable PCI_MSI_IRQ_DOMAIN support for MIPS
  MIPS: BMIPS: add PCI bindings for 7425, 7435
  MIPS: BMIPS: enable PCI
  ARM64: declare __phys_to_dma on ARCH_HAS_PHYS_TO_DMA
  ARM64: add dma remap for BrcmSTB PCIe
  ARM: add dma remap for BrcmSTB PCIe

 .../devicetree/bindings/pci/brcmstb-pcie.txt       |   59 +
 arch/arm/Kconfig                                   |   33 +
 arch/arm/configs/brcmstb_defconfig                 |  204 +++
 arch/arm/configs/multi_v7_defconfig                |    3 -
 arch/arm/mach-bcm/Kconfig                          |   21 +-
 arch/arm/mach-bcm/Makefile.boot                    |    0
 arch/arm/mach-bcm/include/mach/irqs.h              |    3 +
 arch/arm/mach-bcm/include/mach/memory.h            |   47 +
 arch/arm/mach-bcm/include/mach/uncompress.h        |    8 +
 arch/arm64/include/asm/dma-direct.h                |   16 +
 arch/mips/Kconfig                                  |    3 +
 arch/mips/bmips/dma.c                              |    9 +
 arch/mips/boot/dts/brcm/bcm7425.dtsi               |   28 +
 arch/mips/boot/dts/brcm/bcm7435.dtsi               |   28 +
 arch/mips/boot/dts/brcm/bcm97425svmb.dts           |    4 +
 arch/mips/boot/dts/brcm/bcm97435svmb.dts           |    4 +
 drivers/pci/Kconfig                                |    2 +-
 drivers/pci/controller/Kconfig                     |   13 +
 drivers/pci/controller/Makefile                    |    1 +
 drivers/pci/controller/pcie-brcmstb.c              | 1554 ++++++++++++++++++++
 drivers/soc/bcm/brcmstb/Makefile                   |    2 +-
 drivers/soc/bcm/brcmstb/memory.c                   |  158 ++
 include/soc/brcmstb/common.h                       |   16 +
 include/soc/brcmstb/memory_api.h                   |   26 +
 24 files changed, 2217 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt
 create mode 100644 arch/arm/configs/brcmstb_defconfig
 create mode 100644 arch/arm/mach-bcm/Makefile.boot
 create mode 100644 arch/arm/mach-bcm/include/mach/irqs.h
 create mode 100644 arch/arm/mach-bcm/include/mach/memory.h
 create mode 100644 arch/arm/mach-bcm/include/mach/uncompress.h
 create mode 100644 arch/arm64/include/asm/dma-direct.h
 create mode 100644 drivers/pci/controller/pcie-brcmstb.c
 create mode 100644 drivers/soc/bcm/brcmstb/memory.c
 create mode 100644 include/soc/brcmstb/memory_api.h

-- 
1.9.0.138.g2de3478

[PATCH v5 08/12] MIPS: BMIPS: add PCI bindings for 7425, 7435

[Jim Quinlan]

Adds the PCIe nodes for the Broadcom STB PCIe root complex.

Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7425.dtsi     | 28 ++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm7435.dtsi     | 28 ++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97425svmb.dts |  4 ++++
 arch/mips/boot/dts/brcm/bcm97435svmb.dts |  4 ++++
 4 files changed, 64 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index 410e61e..0edcbe4 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -584,4 +584,32 @@
 			};
 		};
 	};
+
+	pcie: pcie@10410000 {
+		reg = <0x10410000 0x830c>;
+		compatible = "brcm,bcm7425-pcie";
+		interrupts = <37>, <37>;
+		interrupt-names = "pcie", "msi";
+		interrupt-parent = <&periph_intc>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		linux,pci-domain = <0>;
+		brcm,enable-ssc;
+		bus-range = <0x00 0xff>;
+		msi-controller;
+		#interrupt-cells = <1>;
+		/* 4x128mb windows */
+		ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0x0 0x20000000>;
+		/* 768M or 1GB memc0, 0-1GB memc1 */
+		dma-ranges =
+			<0x02000000 0x0 0x00000000 0x00000000 0x0 0x10000000>,
+			<0x02000000 0x0 0x10000000 0x20000000 0x0 0x30000000>,
+			<0x02000000 0x0 0x40000000 0x90000000 0x0 0x40000000>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &periph_intc 33
+				 0 0 0 2 &periph_intc 34
+				 0 0 0 3 &periph_intc 35
+				 0 0 0 4 &periph_intc 36>;
+	};
+
 };
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 8398b7f..50bc7a0 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -599,4 +599,32 @@
 			};
 		};
 	};
+
+	pcie: pcie@10410000 {
+		reg = <0x10410000 0x930c>;
+		interrupts = <0x27>, <0x27>;
+		interrupt-names = "pcie", "msi";
+		interrupt-parent = <&periph_intc>;
+		compatible = "brcm,bcm7435-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		linux,pci-domain = <0>;
+		brcm,enable-ssc;
+		bus-range = <0x00 0xff>;
+		msi-controller;
+		#interrupt-cells = <1>;
+		ranges = <0x2000000 0x0 0xd0000000 0xd0000000 0x0 0x20000000>;
+		/* 768M or 1GB memc0, 0-1GB memc1 */
+		dma-ranges =
+			<0x02000000 0x0 0x00000000 0x00000000 0x0 0x10000000>,
+			<0x02000000 0x0 0x10000000 0x20000000 0x0 0x30000000>,
+			<0x02000000 0x0 0x40000000 0x90000000 0x0 0x40000000>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &periph_intc 35
+				 0 0 0 2 &periph_intc 36
+				 0 0 0 3 &periph_intc 37
+				 0 0 0 4 &periph_intc 38>;
+		status = "disabled";
+	};
+
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index 0ed2221..22270a9 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -152,3 +152,7 @@
 &waketimer {
 	status = "okay";
 };
+
+&pcie {
+	status = "okay";
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index 2c145a8..91bc1ec 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -128,3 +128,7 @@
 &waketimer {
 	status = "okay";
 };
+
+&pcie {
+	status = "okay";
+};
-- 
1.9.0.138.g2de3478

Re: [PATCH v5 08/12] MIPS: BMIPS: add PCI bindings for 7425, 7435

[Paul Burton]

Hi Jim,

On Thu, Sep 06, 2018 at 04:42:57PM -0400, Jim Quinlan wrote:
> Adds the PCIe nodes for the Broadcom STB PCIe root complex.
> 
> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> ---
>  arch/mips/boot/dts/brcm/bcm7425.dtsi     | 28 ++++++++++++++++++++++++++++
>  arch/mips/boot/dts/brcm/bcm7435.dtsi     | 28 ++++++++++++++++++++++++++++
>  arch/mips/boot/dts/brcm/bcm97425svmb.dts |  4 ++++
>  arch/mips/boot/dts/brcm/bcm97435svmb.dts |  4 ++++
>  4 files changed, 64 insertions(+)

Do you have a preference for how this gets merged? If it goes via the
PCI tree then for patches 8 & 9:

    Acked-by: Paul Burton <paul.burton@mips.com>

Still looking at patch 6.

Thanks,
    Paul

Re: [PATCH v5 08/12] MIPS: BMIPS: add PCI bindings for 7425, 7435

[Jim Quinlan]

On Thu, Sep 6, 2018 at 5:50 PM Paul Burton <paul.burton@mips.com> wrote:
>
> Hi Jim,
>
> On Thu, Sep 06, 2018 at 04:42:57PM -0400, Jim Quinlan wrote:
> > Adds the PCIe nodes for the Broadcom STB PCIe root complex.
> >
> > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
> > ---
> >  arch/mips/boot/dts/brcm/bcm7425.dtsi     | 28 ++++++++++++++++++++++++++++
> >  arch/mips/boot/dts/brcm/bcm7435.dtsi     | 28 ++++++++++++++++++++++++++++
> >  arch/mips/boot/dts/brcm/bcm97425svmb.dts |  4 ++++
> >  arch/mips/boot/dts/brcm/bcm97435svmb.dts |  4 ++++
> >  4 files changed, 64 insertions(+)
>
> Do you have a preference for how this gets merged? If it goes via the
> PCI tree then for patches 8 & 9:
>
>     Acked-by: Paul Burton <paul.burton@mips.com>
>
Hi Paul,

I hope that the 12 commits  go together and will go through the PCI
tree.  I'm inclined to think I will have to do a V6, and in the cover
leter I will mention this request.

Thanks!
Jim

> Still looking at patch 6.
>
> Thanks,
>     Paul

Re: [PATCH v5 08/12] MIPS: BMIPS: add PCI bindings for 7425, 7435

[Jonas Gorski]

On 10 September 2018 at 16:37, Jim Quinlan <jim2101024@gmail.com> wrote:
> On Thu, Sep 6, 2018 at 5:50 PM Paul Burton <paul.burton@mips.com> wrote:
>>
>> Hi Jim,
>>
>> On Thu, Sep 06, 2018 at 04:42:57PM -0400, Jim Quinlan wrote:
>> > Adds the PCIe nodes for the Broadcom STB PCIe root complex.
>> >
>> > Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
>> > ---
>> >  arch/mips/boot/dts/brcm/bcm7425.dtsi     | 28 ++++++++++++++++++++++++++++
>> >  arch/mips/boot/dts/brcm/bcm7435.dtsi     | 28 ++++++++++++++++++++++++++++
>> >  arch/mips/boot/dts/brcm/bcm97425svmb.dts |  4 ++++
>> >  arch/mips/boot/dts/brcm/bcm97435svmb.dts |  4 ++++
>> >  4 files changed, 64 insertions(+)
>>
>> Do you have a preference for how this gets merged? If it goes via the
>> PCI tree then for patches 8 & 9:
>>
>>     Acked-by: Paul Burton <paul.burton@mips.com>
>>
> Hi Paul,
>
> I hope that the 12 commits  go together and will go through the PCI
> tree.  I'm inclined to think I will have to do a V6, and in the cover
> leter I will mention this request.

Somehow nothing of the v5 patch series seem to have made it to any
mailing lists, at least I can't find them in my inbox (or spam) in any
of the mailing lists, nor through the public archives of e.g. LKML.
Patchwork (ozlabs and kernel) doesn't know of them either.


Regards
Jonas

Re: [PATCH v5 08/12] MIPS: BMIPS: add PCI bindings for 7425, 7435

[Florian Fainelli]

On 9/12/2018 7:36 AM, Jonas Gorski wrote:
> On 10 September 2018 at 16:37, Jim Quinlan <jim2101024@gmail.com> wrote:
>> On Thu, Sep 6, 2018 at 5:50 PM Paul Burton <paul.burton@mips.com> wrote:
>>>
>>> Hi Jim,
>>>
>>> On Thu, Sep 06, 2018 at 04:42:57PM -0400, Jim Quinlan wrote:
>>>> Adds the PCIe nodes for the Broadcom STB PCIe root complex.
>>>>
>>>> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
>>>> ---
>>>>   arch/mips/boot/dts/brcm/bcm7425.dtsi     | 28 ++++++++++++++++++++++++++++
>>>>   arch/mips/boot/dts/brcm/bcm7435.dtsi     | 28 ++++++++++++++++++++++++++++
>>>>   arch/mips/boot/dts/brcm/bcm97425svmb.dts |  4 ++++
>>>>   arch/mips/boot/dts/brcm/bcm97435svmb.dts |  4 ++++
>>>>   4 files changed, 64 insertions(+)
>>>
>>> Do you have a preference for how this gets merged? If it goes via the
>>> PCI tree then for patches 8 & 9:
>>>
>>>      Acked-by: Paul Burton <paul.burton@mips.com>
>>>
>> Hi Paul,
>>
>> I hope that the 12 commits  go together and will go through the PCI
>> tree.  I'm inclined to think I will have to do a V6, and in the cover
>> leter I will mention this request.
> 
> Somehow nothing of the v5 patch series seem to have made it to any
> mailing lists, at least I can't find them in my inbox (or spam) in any
> of the mailing lists, nor through the public archives of e.g. LKML.
> Patchwork (ozlabs and kernel) doesn't know of them either.

Indeed, that would explain why there has been little discussion on this....
-- 
Florian