From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: [PATCH v5 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI Date: Fri, 28 Sep 2018 18:04:33 +0800 Message-ID: <1538129080-8206-3-git-send-email-honghui.zhang@mediatek.com> References: <1538129080-8206-1-git-send-email-honghui.zhang@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1538129080-8206-1-git-send-email-honghui.zhang@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: lorenzo.pieralisi@arm.com, bhelgaas@google.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, ryder.lee@mediatek.com Cc: ulf.hansson@linaro.org, marc.zyngier@arm.com, matthias.bgg@gmail.com, devicetree@vger.kernel.org, yingjoe.chen@mediatek.com, eddie.huang@mediatek.com, honghui.zhang@mediatek.com, youlin.pei@mediatek.com, yt.shen@mediatek.com, sean.wang@mediatek.com List-Id: devicetree@vger.kernel.org From: Honghui Zhang The PCIe controller of MT7622 has TYPE 1 configuration space type, but the HW default class type values is invalid. The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class type for MT7622") have set the class ID for MT7622 as PCI_CLASS_BRIDGE_HOST, but it's not workable for MT7622: In __pci_bus_assign_resources, the framework only setup bridge's resource window only if class type is PCI_CLASS_BRIDGE_PCI. Or it will leave the subordinary PCIe device's MMIO window un-touched. Fixup the class type to PCI_CLASS_BRIDGE_PCI as most of the controller driver do. Signed-off-by: Honghui Zhang --- drivers/pci/controller/pcie-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 264e03f..3ab80d6 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -436,7 +436,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val = PCI_VENDOR_ID_MEDIATEK; writew(val, port->base + PCIE_CONF_VEND_ID); - val = PCI_CLASS_BRIDGE_HOST; + val = PCI_CLASS_BRIDGE_PCI; writew(val, port->base + PCIE_CONF_CLASS_ID); } -- 2.6.4