From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver Date: Mon, 04 Nov 2013 13:26:44 +0100 Message-ID: <1539581.zprt32081v@amdc1227> References: <1383205544-32244-1-git-send-email-gautam.vivek@samsung.com> <1383205544-32244-2-git-send-email-gautam.vivek@samsung.com> <527744B2.4090303@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Return-path: In-reply-to: <527744B2.4090303@ti.com> Sender: linux-doc-owner@vger.kernel.org To: Kishon Vijay Abraham I Cc: Vivek Gautam , linux-usb@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, gregkh@linuxfoundation.org, kgene.kim@samsung.com, k.debski@samsung.com, s.nawrocki@samsung.com, balbi@ti.com, jwerner@chromium.org, jg1.han@samsung.com List-Id: devicetree@vger.kernel.org Hi Kishon, On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote: > Hi Vivek, > > On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote: > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. > > The new driver uses the generic PHY framework and will interact > > with DWC3 controller present on Exynos5 series of SoCs. > > In Exynos, you have a single IP that supports both USB3 and USB2 PHY > right? I think that needs to be mentioned here. Nope. There are two separate, different IPs. > Do you have separate registers that should be used for > initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If > so, then you should model this driver as a single driver that supports > two PHYs similar to what Sylwester has done before? Sylwester's MIPI PHY uses such model because it has a single register that controls both PHYs. Best regards, Tomasz