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a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1736419756; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tVp/68k41NkFcAhuu7KioYy3MSHOTjh5xj32/pjsGg4=; b=kIxlrJylsUFKd9k4Ug86GqQ8f1FamKE6IjXoic8MT26rz0nZAbIK7svuRMcr3ki5JDpbus NetzVPx9ArCf5zpUoAIrw654dEfrLbkpVbzDlAB/xBo2yN73oIJ5/fJ99j0kW6wsZcZ4Vl MLYHMAYphVJZxFvfon/b0XxLJxRjAFYOhO5RuRf4V2XzLtOAT0mLBzPAU2qBnuthDicWFh eNvHZEjxTvJ2XUaAp2tCDJfy0Jh8tAvcYUqvNnECT3Kn/LtrMm4MdNIvFVloCsqYk6cmNn 2pOc/pEdvKQCm0e+u0iXvV6F65J6rLYvCJ3yowc5taUUNwZm1FhqzoRB3uNadg== From: Alexander Stein To: Herve Codina Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Louis Chauvet , Luca Ceresoli , Thomas Petazzoni Subject: Re: [PATCH v3 3/3] drm: bridge: ti-sn65dsi83: Add error recovery mechanism Date: Thu, 09 Jan 2025 11:49:13 +0100 Message-ID: <15398572.tv2OnDr8pf@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20250108184442.64f38fbc@bootlin.com> References: <20250108101907.410456-1-herve.codina@bootlin.com> <115787605.nniJfEyVGO@steina-w> <20250108184442.64f38fbc@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Last-TLS-Session-Version: TLSv1.3 Hi Herve, Am Mittwoch, 8. Januar 2025, 18:44:42 CET schrieb Herve Codina: > Hi Alexander, >=20 > On Wed, 08 Jan 2025 11:54:49 +0100 > Alexander Stein wrote: >=20 > [...] > > > #include > > > #include > > > +#include /* DRM_MODESET_LOCK_ALL_BEGIN() needs drm_d= rv_uses_atomic_modeset() */ =20 > >=20 > > Shouldn't this include be added to include/drm/drm_modeset_lock.h inste= ad? >=20 > Yes indeed. I will change that in the next iteration. >=20 > >=20 > > > #include > > > #include > > > #include > > > @@ -147,6 +150,9 @@ struct sn65dsi83 { > > > struct regulator *vcc; > > > bool lvds_dual_link; > > > bool lvds_dual_link_even_odd_swap; > > > + bool use_irq; > > > + struct delayed_work monitor_work; > > > + struct work_struct reset_work; =20 > >=20 > > Can you please rebase? You are missing commit d2b8c6d549570 > > ("drm/bridge: ti-sn65dsi83: Add ti,lvds-vod-swing optional properties") >=20 > Sure, I will rebase. >=20 > [...] > > > +static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx) > > > +{ > > > + unsigned int irq_stat; > > > + int ret; > > > + > > > + /* > > > + * Schedule a reset in case of: > > > + * - the bridge doesn't answer > > > + * - the bridge signals an error > > > + */ > > > + > > > + ret =3D regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat); > > > + if (ret || irq_stat) > > > + schedule_work(&ctx->reset_work); =20 > >=20 > > Shouldn't you clear the error bits as well? >=20 > Thanks for pointing that. >=20 > I can clear the error bit but further more, I probably need to simply > disable the interrupt. >=20 > In some cases, we observed i2c access failure. In that cases clearing err= or > bits is simply not possible. >=20 > To avoid some possible interrupt storms (the chip detect a failure, set i= ts > interrupt line but could be not accessible anymore), the best thing to do > is to disable the interrupt line here, let the reset work to do its job > performing a full reset of the device and re-enabling the interrupt line > when needed, probably in sn65dsi83_atomic_enable(). >=20 > What do you think about that? As I read the datasheet this is a active-high level interrupt, so as long as some enabled IRQs are pending the signal will stay high. There are 3 notes in section 9.1.3. IRQ usage that in various situations IRQ bits may be set/pending and have to be cleared. At least clear the interrupts before enabling it again to be on the safe side. Best regards, Alexander =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/