[PATCH v4 0/3]

[PATCH v4 0/3]

[Jeykumar Sankaran]

Reviving the patch posted by Sean initially.

This patch set adds MDSS and DSI nodes to SDM845 dtsi to enable display. The
patches are tested on SDM845 MTP platform using the kernel based on [1].

Part of the dependent drivers are already posted on list. Rest of the
dependencies are met using using downstream version of the driver(s) which are
yet to make it to the list. 

References to the driver patches used for testing:

display controller: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/arch/arm64/boot/dts/qcom/sdm845.dtsi?id=40019e8452fe76867bdb2e7
WLED: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=11023&archive=both&state=*
Panel: https://patchwork.freedesktop.org/series/50657/
iommu: https://patchwork.kernel.org/patch/10534999/

[1] https://git.linaro.org/landing-teams/working/qualcomm/kernel.git/log/?h=integration-linux-qcomlt

Thanks and Regards,
Jeykumar S.

Changes in v4:
	- changes to add pinctrl nodes to SoC dts and display nodes to MTP
	  are included in the series
	- clock name clean up in dsi nodes
	- move around added nodes to maintain naming orders

Jeykumar Sankaran (3):
  arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file
  arm64: dts: sdm845: Add dsi pinctrl nodes
  arm64: dts: sdm845: Add display nodes to MTP dts

 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 124 +++++++++++++++++++
 arch/arm64/boot/dts/qcom/sdm845.dtsi    | 205 ++++++++++++++++++++++++++++++++
 2 files changed, 329 insertions(+)

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[PATCH v4 2/3] arm64: dts: sdm845: Add dsi pinctrl nodes

[Jeykumar Sankaran]

Add dsi active/suspend pinctrl nodes to sdm845 SoC dts.

Changes in v4:
	- patch introduced in the series

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 5728b4c..35df5d2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -822,6 +822,20 @@
 			interrupt-controller;
 			#interrupt-cells = <2>;
 
+			dpu_dsi_active: dpu-dsi-active {
+				pinmux {
+					pins = "gpio6", "gpio52";
+					function = "gpio";
+				};
+			};
+
+			dpu_dsi_suspend: dpu-dsi-suspend {
+				pinmux {
+					pins = "gpio6", "gpio52";
+					function = "gpio";
+				};
+			};
+
 			qup_i2c0_default: qup-i2c0-default {
 				pinmux {
 					pins = "gpio0", "gpio1";
-- 
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Re: [PATCH v4 2/3] arm64: dts: sdm845: Add dsi pinctrl nodes

[Doug Anderson]

Hi (sending again since I screwed up my previous reply),

On Fri, Nov 2, 2018 at 3:26 PM Jeykumar Sankaran <jsanka@codeaurora.org> wrote:
>
> Add dsi active/suspend pinctrl nodes to sdm845 SoC dts.
>
> Changes in v4:
>         - patch introduced in the series
>
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 5728b4c..35df5d2 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -822,6 +822,20 @@
>                         interrupt-controller;
>                         #interrupt-cells = <2>;
>
> +                       dpu_dsi_active: dpu-dsi-active {
> +                               pinmux {
> +                                       pins = "gpio6", "gpio52";
> +                                       function = "gpio";
> +                               };
> +                       };
> +
> +                       dpu_dsi_suspend: dpu-dsi-suspend {
> +                               pinmux {
> +                                       pins = "gpio6", "gpio52";
> +                                       function = "gpio";
> +                               };
> +                       };
> +

Ugh, I should have noticed this in my previous reply.  Sorry!

...looking closer I see that these two pins are MTP-specific.  They
belong fully in the MTP device tree file.  Other sdm845 boards won't
necessarily have the same functions on the same pins so they don't
belong here in the SoC file.

Also as a note: once you move them there they should no longer go in
the section "PINCTRL - additions to nodes defined in sdm845.dtsi".
They should go under the tlmm in the section "PINCTRL - board-specific
pinctrl".  Please make sure they are alphabetical there.

Since these are board specific, node names should be based on the
schematic name.  ...and in this case since they are two distinct named
pins I'd probably have a separate node for each one.  So I think you
want something like this in the mtp file: (untested)

disp_mode_sel_active: disp-mode-sel-active {
  pinmux {
    pins = "gpio52";
    function = "gpio";
  };
  pinconf {
    pins = "gpio52";
    drive-strength = <8>;
    bias-disable;
};

disp_mode_sel_sleep: disp-mode-sel-sleep {
  pinmux {
    pins = "gpio52";
    function = "gpio";
  };
  pinconf {
    pins = "gpio52";
    drive-strength = <2>;
    bias-pull-down;
};

...and then one for gpio6:

lcd0_reset_n_active: lcd0-reset-n-active {
  ...
};

---

I'm kinda curious if the sleep stuff is all truly necessary though.
Specifically I don't _think_ that the pulls are affected by the drive
strength.  So either we continue driving this pin while we're sleeping
in which case the drive strength matters and the pull doesn't.  ...or
we aren't driving it in sleep and the pull might matter but the drive
strength doesn't.

I definitely see a lot of this cruft coming from the Qualcomm
downstream without anyone who can explain to me that it's useful.  It
seems like everyone just blindly copies it from someone else.  As
further evidence that this isn't currently doing anything, as far as I
can tell the v10 panel driver for this panel doesn't actually even
select the suspend state.

Maybe we can just drop the whole "active" vs. "sleep" for now and we
can introduce it later when we show that it's useful for something.
Then we can confirm if it's the drive strength that's useful or the
pull down and we can also confirm that we don't end up going to sleep
with the pin being driven in the opposite direction of the pull.

Maybe +Bjorn or +Stephen has a different opinion though...

-Doug
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Re: [PATCH v4 2/3] arm64: dts: sdm845: Add dsi pinctrl nodes

[Bjorn Andersson]

On Tue 06 Nov 16:31 PST 2018, Doug Anderson wrote:
[..]
> Maybe we can just drop the whole "active" vs. "sleep" for now and we
> can introduce it later when we show that it's useful for something.
[..]
> Maybe +Bjorn or +Stephen has a different opinion though...
> 

This sounds like a good suggestion, in particular we know that it won't
break like SPI did once we select the "sleep" state sometime in the
future.

Regards,
Bjorn
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[PATCH v4 1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Jeykumar Sankaran]

DPU is short for the Display Processing Unit. It is the display
controller on Qualcomm SDM845 chips.

This change adds MDSS and DSI nodes to enable display on the
target device.

Changes in v2:
	 - Beefed up commit message
	 - Use SoC specific compatibles for mdss and dpu (Rob H)
	 - Use assigned-clocks to set initial clock frequency(Rob H)
Changes in v3:
	 - added IOMMU node
	 - Fix device naming (remove _phys)
	 - Use correct IRQ_TYPE in interrupt specifiers
Changes in v4:
	 - move mdss node to preserve the unit address sort order
	 - remove _clk suffix from dsi clocks
	 (both the comments are from Doug Anderson)

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 191 +++++++++++++++++++++++++++++++++++
 1 file changed, 191 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b72bdb0..5728b4c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1248,6 +1248,197 @@
 			};
 		};
 
+		mdss: mdss@ae00000 {
+			compatible = "qcom,sdm845-mdss";
+			reg = <0xae00000 0x1000>;
+			reg-names = "mdss";
+
+			power-domains = <&dispcc 0>;
+
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&gcc GCC_DISP_AXI_CLK>,
+				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
+			clock-names = "iface", "bus", "core";
+
+			assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+			assigned-clock-rates = <300000000>;
+
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			iommus = <&apps_smmu 0x880 0x8>,
+			         <&apps_smmu 0xc80 0x8>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdss_mdp: mdp@ae01000 {
+				compatible = "qcom,sdm845-dpu";
+				reg = <0x0ae01000 0x8f000>,
+				      <0x0aeb0000 0x2008>;
+				reg-names = "mdp", "vbif";
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>,
+					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "iface", "bus", "core", "vsync";
+
+				assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+						  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <300000000>,
+						       <19200000>;
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dpu_intf1_out: endpoint {
+							remote-endpoint = <&dsi0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dpu_intf2_out: endpoint {
+							remote-endpoint = <&dsi1_in>;
+						};
+					};
+				};
+			};
+
+			dsi0: dsi@ae94000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae94000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				phys = <&dsi0_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi0_in: endpoint {
+							remote-endpoint = <&dpu_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi0_phy: dsi-phy@ae94400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae94400 0x200>,
+				      <0xae94a00 0x1e0>,
+				      <0xae94600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface";
+			};
+
+			dsi1: dsi@ae96000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0xae96000 0x400>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+				clock-names = "byte",
+					      "byte_intf",
+					      "pixel",
+					      "core",
+					      "iface",
+					      "bus";
+
+				phys = <&dsi1_phy>;
+				phy-names = "dsi-phy";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi1_in: endpoint {
+							remote-endpoint = <&dpu_intf2_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi1_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi1_phy: dsi-phy@ae96400 {
+				compatible = "qcom,dsi-phy-10nm";
+				reg = <0xae96400 0x200>,
+				      <0xae96a00 0x10e>,
+				      <0xae96600 0x280>;
+				reg-names = "dsi_phy",
+					    "dsi_pll",
+					    "dsi_phy_lane";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "iface";
+			};
+		};
+
 		dispcc: clock-controller@af00000 {
 			compatible = "qcom,sdm845-dispcc";
 			reg = <0xaf00000 0x10000>;
-- 
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Re: [PATCH v4 1/3] arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file

[Doug Anderson]

Hi,

On Fri, Nov 2, 2018 at 3:26 PM Jeykumar Sankaran <jsanka@codeaurora.org> wrote:
>
> DPU is short for the Display Processing Unit. It is the display
> controller on Qualcomm SDM845 chips.
>
> This change adds MDSS and DSI nodes to enable display on the
> target device.
>
> Changes in v2:
>          - Beefed up commit message
>          - Use SoC specific compatibles for mdss and dpu (Rob H)
>          - Use assigned-clocks to set initial clock frequency(Rob H)
> Changes in v3:
>          - added IOMMU node
>          - Fix device naming (remove _phys)
>          - Use correct IRQ_TYPE in interrupt specifiers
> Changes in v4:
>          - move mdss node to preserve the unit address sort order
>          - remove _clk suffix from dsi clocks
>          (both the comments are from Doug Anderson)
>
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 191 +++++++++++++++++++++++++++++++++++
>  1 file changed, 191 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index b72bdb0..5728b4c 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1248,6 +1248,197 @@
>                         };
>                 };
>
> +               mdss: mdss@ae00000 {
> +                       compatible = "qcom,sdm845-mdss";
> +                       reg = <0xae00000 0x1000>;
> +                       reg-names = "mdss";
> +
> +                       power-domains = <&dispcc 0>;

Could be done in a follow-up patch, but technically the above should be:

power-domains = <&dispcc MDSS_GDSC>;


> +                       dsi0: dsi@ae94000 {
> +                               compatible = "qcom,mdss-dsi-ctrl";
> +                               reg = <0xae94000 0x400>;
> +                               reg-names = "dsi_ctrl";
> +
> +                               interrupt-parent = <&mdss>;
> +                               interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

Just out of curiousity, where does the 4 comes from?  I guess this matches:

#define MDSS_HW_INTR_STATUS_INTR_DSI0                           0x00000010
#define MDSS_HW_INTR_STATUS_INTR_DSI1                           0x00000020

...where 0x10 == (1 << 4)

I don't see any bindings for this define so I guess hardcoding it is
fine (and the 5 for DSI1).


> +                       dsi0_phy: dsi-phy@ae94400 {
> +                               compatible = "qcom,dsi-phy-10nm";
> +                               reg = <0xae94400 0x200>,
> +                                     <0xae94a00 0x1e0>,
> +                                     <0xae94600 0x280>;
> +                               reg-names = "dsi_phy",
> +                                           "dsi_pll",
> +                                           "dsi_phy_lane";
> +
> +                               #clock-cells = <1>;
> +                               #phy-cells = <0>;
> +
> +                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
> +                               clock-names = "iface";
> +                       };

+Matthias will probably want to base a future patch on this one since
he's trying to hook the clocks up more properly.  ...but what you have
above matches the current bindings so I think we're good.


Overall: I am not massively familiar with display / bridge / panel
bindings but as far as I can tell this patch is good and ready to
land.  Future work (like fixing the nit about using the power domain
#define) can always be done in a follow-up patch.  Thus:

Reviewed-by: Douglas Anderson <dianders@chromium.org>

I've tested this patch and it's helped me get a working display.  Thus:

Tested-by: Douglas Anderson <dianders@chromium.org>

-Doug
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[PATCH v4 3/3] arm64: dts: sdm845: Add display nodes to MTP dts

[Jeykumar Sankaran]

Add mdss, dsi, dsi_phy, dsi pinctrl  and truly nt35597 panel nodes to
sdm845 MTP board dtsi.

Changes in v4:
	- patch introduced in the series
	- move around added nodes to preserve alphabetical order (Doug Anderson)

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 124 ++++++++++++++++++++++++++++++++
 1 file changed, 124 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index eedfaf8..eb2a05b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sdm845.dtsi"
 
@@ -343,11 +344,118 @@
 	};
 };
 
+&dsi0 {
+	status = "okay";
+	qcom,dual-dsi-mode;
+	qcom,master-dsi;
+	qcom,sync-dual-dsi;
+
+	vdda-supply = <&vdda_mipi_dsi0_1p2>;
+
+	panel@0 {
+		compatible = "truly,nt35597-2K-display";
+		reg = <0>;
+
+		vdda-supply = <&vreg_l14a_1p88>;
+		vdispp-supply = <&lab_regulator>;
+		vdispn-supply = <&ibb_regulator>;
+
+		pinctrl-names = "default", "suspend";
+		pinctrl-0 = <&dpu_dsi_active>;
+		pinctrl-1 = <&dpu_dsi_suspend>;
+
+		reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+		mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+
+		display-timings {
+			timing0: timing-0 {
+				/* originally
+				 * 268316160 Mhz,
+				 * but value below fits
+				 * better w/ downstream
+				 */
+				clock-frequency = <268316138>;
+				hactive = <1440>;
+				vactive = <2560>;
+				hfront-porch = <200>;
+				hback-porch = <64>;
+				hsync-len = <32>;
+				vfront-porch = <8>;
+				vback-porch = <7>;
+				vsync-len = <1>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				panel0_in: endpoint {
+					remote-endpoint = <&dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				panel1_in: endpoint {
+					remote-endpoint = <&dsi1_out>;
+				};
+			};
+		};
+	};
+
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&panel0_in>;
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&dsi0_phy {
+	status = "okay";
+	vdds-supply = <&vdda_mipi_dsi0_pll>;
+};
+
+&dsi1 {
+	status = "okay";
+
+	qcom,dual-dsi-mode;
+	qcom,sync-dual-dsi;
+
+	vdda-supply = <&vdda_mipi_dsi1_1p2>;
+
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&panel1_in>;
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&dsi1_phy {
+	status = "okay";
+	vdds-supply = <&vdda_mipi_dsi1_pll>;
+};
+
 &i2c10 {
 	status = "okay";
 	clock-frequency = <400000>;
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_mdp {
+	status = "okay";
+};
+
 &qupv3_id_1 {
 	status = "okay";
 };
@@ -419,6 +527,22 @@
 
 /* PINCTRL - additions to nodes defined in sdm845.dtsi */
 
+&dpu_dsi_active {
+	pinconf {
+		pins = "gpio6", "gpio52";
+		drive-strength = <8>;
+		bias-disable;
+	};
+};
+
+&dpu_dsi_suspend {
+	pinconf {
+		pins = "gpio6", "gpio52";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+};
+
 &qup_i2c10_default {
 	pinconf {
 		pins = "gpio55", "gpio56";
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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