* [PATCH V5 4/6] dts: imx: add common imx7ulp dtsi support
[not found] <1541862478-7839-1-git-send-email-aisheng.dong@nxp.com>
2018-11-10 15:12 ` [PATCH V5 1/6] dt-bindings: fsl: add compatible for imx7ulp evk A.s. Dong
2018-11-10 15:13 ` [PATCH V5 2/6] dt-bindings: fsl: add imx7ulp pm related components bindings A.s. Dong
@ 2018-11-10 15:13 ` A.s. Dong
2018-11-10 15:52 ` Fabio Estevam
2018-12-06 14:51 ` Shawn Guo
2018-11-10 15:13 ` [PATCH V5 5/6] dts: fsl: add imx7ulp evk support A.s. Dong
3 siblings, 2 replies; 11+ messages in thread
From: A.s. Dong @ 2018-11-10 15:13 UTC (permalink / raw)
To: linux-arm-kernel@lists.infradead.org
Cc: A.s. Dong, devicetree@vger.kernel.org, dongas86@gmail.com,
linux@armlinux.org.uk, robh+dt@kernel.org, dl-linux-imx,
kernel@pengutronix.de, Fabio Estevam, shawnguo@kernel.org
The i.MX 7ULP family of processors features NXP's advanced implementation
of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
Graphics Processing Units (GPUs).
This patch aims to add the initial support including:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v4->v5:
* add input clocks for PCC module
v3->v4:
* no changes
v2->v3:
* change to generic node names
* remove arch timer due to:
1) arch timer is fixed to 1Mhz which is lower accurate than TPM timer (3Mhz).
2) no firmware progrem CNTFREQ
3) cpuidle driver is still not in tree will may cause system hang
v1->v2:
* update clk part due to binding change
* separate soc.dtsi from board.dts
---
arch/arm/boot/dts/imx7ulp.dtsi | 346 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 346 insertions(+)
create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..931b275
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ gpio0 = &gpio_ptc;
+ gpio1 = &gpio_ptd;
+ gpio2 = &gpio_pte;
+ gpio3 = &gpio_ptf;
+ i2c0 = &lpi2c6;
+ i2c1 = &lpi2c7;
+ mmc0 = &usdhc0;
+ mmc1 = &usdhc1;
+ serial0 = &lpuart4;
+ serial1 = &lpuart5;
+ serial2 = &lpuart6;
+ serial3 = &lpuart7;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ intc: interrupt-controller@40021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x40021000 0x1000>,
+ <0x40022000 0x1000>;
+ };
+
+ rosc: clock-rosc {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "rosc";
+ #clock-cells = <0>;
+ };
+
+ sosc: clock-sosc {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "sosc";
+ #clock-cells = <0>;
+ };
+
+ sirc: clock-sirc {
+ compatible = "fixed-clock";
+ clock-frequency = <16000000>;
+ clock-output-names = "sirc";
+ #clock-cells = <0>;
+ };
+
+ firc: clock-firc {
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ clock-output-names = "firc";
+ #clock-cells = <0>;
+ };
+
+ upll: clock-upll {
+ compatible = "fixed-clock";
+ clock-frequency = <480000000>;
+ clock-output-names = "upll";
+ #clock-cells = <0>;
+ };
+
+ mpll: clock-mpll {
+ compatible = "fixed-clock";
+ clock-frequency = <480000000>;
+ clock-output-names = "mpll";
+ #clock-cells = <0>;
+ };
+
+ ahbbridge0: bus@40000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40000000 0x800000>;
+ ranges;
+
+ lpuart4: serial@402d0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402d0000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+ clock-names = "ipg";
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+ assigned-clock-rates = <24000000>;
+ status = "disabled";
+ };
+
+ lpuart5: serial@402e0000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x402e0000 0x1000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+ clock-names = "ipg";
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ tpm5: tpm@40260000 {
+ compatible = "fsl,imx7ulp-tpm";
+ reg = <0x40260000 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&pcc2 IMX7ULP_CLK_LPTPM5>;
+ clock-names = "ipg", "per";
+ };
+
+ usdhc0: mmc@40370000 {
+ compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x40370000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC0>;
+ clock-names ="ipg", "ahb", "per";
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc1: mmc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ scg1: clock-controller@403e0000 {
+ compatible = "fsl,imx7ulp-scg1";
+ reg = <0x403e0000 0x10000>;
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>, <&mpll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll", "mpll";
+ #clock-cells = <1>;
+ };
+
+ pcc2: clock-controller@403f0000 {
+ compatible = "fsl,imx7ulp-pcc2";
+ reg = <0x403f0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&scg1 IMX7ULP_CLK_DDR_DIV>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+ <&scg1 IMX7ULP_CLK_UPLL>,
+ <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_MIPI_PLL>,
+ <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_ROSC>,
+ <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+ "apll_pfd2", "apll_pfd1", "apll_pfd0",
+ "upll", "sosc_bus_clk", "mpll",
+ "firc_bus_clk", "rosc", "spll_bus_clk";
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+ };
+
+ smc1: smc1@40410000 {
+ compatible = "fsl,imx7ulp-smc1";
+ reg = <0x40410000 0x1000>;
+ };
+
+ pcc3: clock-controller@40b30000 {
+ compatible = "fsl,imx7ulp-pcc3";
+ reg = <0x40b30000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&scg1 IMX7ULP_CLK_DDR_DIV>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+ <&scg1 IMX7ULP_CLK_UPLL>,
+ <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_MIPI_PLL>,
+ <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_ROSC>,
+ <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+ "apll_pfd2", "apll_pfd1", "apll_pfd0",
+ "upll", "sosc_bus_clk", "mpll",
+ "firc_bus_clk", "rosc", "spll_bus_clk";
+ };
+ };
+
+ ahbbridge1: bus@40800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40800000 0x800000>;
+ ranges;
+
+ lpi2c6: i2c@40a40000 {
+ compatible = "fsl,imx7ulp-lpi2c";
+ reg = <0x40a40000 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+ clock-names = "ipg";
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ lpi2c7: i2c@40a50000 {
+ compatible = "fsl,imx7ulp-lpi2c";
+ reg = <0x40a50000 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+ clock-names = "ipg";
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ lpuart6: serial@40a60000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x40a60000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+ clock-names = "ipg";
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ lpuart7: serial@40a70000 {
+ compatible = "fsl,imx7ulp-lpuart";
+ reg = <0x40a70000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
+ clock-names = "ipg";
+ assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+ assigned-clock-rates = <48000000>;
+ status = "disabled";
+ };
+
+ iomuxc1: pinctrl@40ac0000 {
+ compatible = "fsl,imx7ulp-iomuxc1";
+ reg = <0x40ac0000 0x1000>;
+ };
+
+ gpio_ptc: gpio@40ae0000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLC>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 0 32>;
+ };
+
+ gpio_ptd: gpio@40af0000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40af0000 0x1000 0x400f0040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLD>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 32 32>;
+ };
+
+ gpio_pte: gpio@40b00000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40b00000 0x1000 0x400f0080 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLE>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 64 32>;
+ };
+
+ gpio_ptf: gpio@40b10000 {
+ compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
+ reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+ <&pcc3 IMX7ULP_CLK_PCTLF>;
+ clock-names = "gpio", "port";
+ gpio-ranges = <&iomuxc1 0 96 32>;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH V5 5/6] dts: fsl: add imx7ulp evk support
[not found] <1541862478-7839-1-git-send-email-aisheng.dong@nxp.com>
` (2 preceding siblings ...)
2018-11-10 15:13 ` [PATCH V5 4/6] dts: imx: add common imx7ulp dtsi support A.s. Dong
@ 2018-11-10 15:13 ` A.s. Dong
2018-12-06 14:54 ` Shawn Guo
3 siblings, 1 reply; 11+ messages in thread
From: A.s. Dong @ 2018-11-10 15:13 UTC (permalink / raw)
To: linux-arm-kernel@lists.infradead.org
Cc: A.s. Dong, devicetree@vger.kernel.org, dongas86@gmail.com,
linux@armlinux.org.uk, robh+dt@kernel.org, dl-linux-imx,
kernel@pengutronix.de, Fabio Estevam, shawnguo@kernel.org
The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MX 7ULP, which features NXP's advanced implementation
of the Arm Cortex-A7 core, the Arm Cortex-M4 core, as well as a 3D and
2D Graphics Processing Units (GPUs).
The EVK enables HDMI output for simple out-of-the-box to bring up but
allows reconfiguration for MIPI displays. The EVK is designed as a
System-On-Module(SOM) board that connects to an associated baseboard.
The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card
socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector
and an NXP PF1550 power management IC (PMIC). The baseboard provides
additional capabilities including a full SD/MMC 3.0 card socket, audio
codec, multiple sensors, an HDMI connector, and an alternate MIPI display
connector. Additionally, the EVK facilitates software development with the
ultimate goal of faster time to market through the support of both
Linux OS and AndroidTM rich operating systems, as well as FreeRTOS.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
FEC
SD/MMC
See more board details:
https://www.nxp.com/products/processors-and-microcontrollers/
arm-based-processors-and-mcus/i.mx-applications-processors/
i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications
-processor:MCIMX7ULP-EVK
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v4->v5:
* update pad setting due to missing pull up enabled
(formerly auto done by driver generic pinconfg)
v3->v4:
* no changes
v2->v3:
* remove "Generic DT based system"
* add device_type property for memory node
* back to old pinctrl binding according to SoC maintainer's suggestions
v1->v2:
* switch to SPDX license
* pad name update
* fix Character '_' not recommended in node name
* separate from soc.dtsi file
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx7ulp-evk.dts | 77 +++++++++++++++++++++++++++++++++++++++
2 files changed, 79 insertions(+)
create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d7268ae..39eac9c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,6 +573,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb-sht11.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+ imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..a09026a
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+ model = "NXP i.MX7ULP EVK";
+ compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
+
+ chosen {
+ stdout-path = &lpuart4;
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ reg_vsd_3v3: regulator-vsd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc0_rst>;
+ gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&lpuart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart4>;
+ status = "okay";
+};
+
+&usdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_vsd_3v3>;
+ status = "okay";
+};
+
+&iomuxc1 {
+ pinctrl_lpuart4: lpuart4grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
+ IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
+ >;
+ bias-pull-up;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
+ IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
+ IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
+ IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
+ IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
+ IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
+ IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
+ >;
+ };
+
+ pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
+ fsl,pins = <
+ IMX7ULP_PAD_PTD0__PTD0 0x3
+ >;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread