From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Wahren Subject: [PATCH 1/3] dt-bindings: imx-ocotp: Add i.MX6ULL/ULZ support Date: Tue, 11 Dec 2018 14:51:11 +0100 Message-ID: <1544536273-17909-2-git-send-email-stefan.wahren@i2se.com> References: <1544536273-17909-1-git-send-email-stefan.wahren@i2se.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1544536273-17909-1-git-send-email-stefan.wahren@i2se.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Srinivas Kandagatla , Rob Herring , Mark Rutland , Shawn Guo , Fabio Estevam Cc: Stefan Wahren , devicetree@vger.kernel.org, Sascha Hauer , linux-imx@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Since the i.MX6ULL/ULZ only supports 8 OTP banks we need to introduce a new compatible. Signed-off-by: Stefan Wahren --- Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt index 792bc5f..455ebbb 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt @@ -1,7 +1,7 @@ Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings This binding represents the on-chip eFuse OTP controller found on -i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL and i.MX6SLL SoCs. +i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ and i.MX6SLL SoCs. Required properties: - compatible: should be one of @@ -9,6 +9,7 @@ Required properties: "fsl,imx6sl-ocotp" (i.MX6SL), or "fsl,imx6sx-ocotp" (i.MX6SX), "fsl,imx6ul-ocotp" (i.MX6UL), + "fsl,imx6ull-ocotp" (i.MX6ULL/ULZ), "fsl,imx7d-ocotp" (i.MX7D/S), "fsl,imx6sll-ocotp" (i.MX6SLL), followed by "syscon". -- 2.7.4