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From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atish.patra@wdc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	devicetree@vger.kernel.org,
	Dmitriy Cherkasov <dmitriy@oss-tech.org>,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Anup Patel <anup@brainfault.org>,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	Christoph Hellwig <hch@infradead.org>
Subject: [PATCH v2 3/4] RISC-V: Remove per cpu clocksource
Date: Thu, 13 Dec 2018 15:14:28 -0800	[thread overview]
Message-ID: <1544742869-19980-4-git-send-email-atish.patra@wdc.com> (raw)
In-Reply-To: <1544742869-19980-1-git-send-email-atish.patra@wdc.com>

There is only one clocksource in RISC-V. The boot cpu initializes
that clocksource. No need to keep a percpu data structure.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
 drivers/clocksource/riscv_timer.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
index 75262409..c9e65086 100644
--- a/drivers/clocksource/riscv_timer.c
+++ b/drivers/clocksource/riscv_timer.c
@@ -49,7 +49,7 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
 	return get_cycles64();
 }
 
-static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
+static struct clocksource riscv_clocksource = {
 	.name		= "riscv_clocksource",
 	.rating		= 300,
 	.mask		= CLOCKSOURCE_MASK(BITS_PER_LONG),
@@ -115,7 +115,6 @@ static void __init riscv_timebase_frequency(struct device_node *node,
 static int __init riscv_timer_init_dt(struct device_node *n)
 {
 	int cpuid, hartid, error;
-	struct clocksource *cs;
 
 	hartid = riscv_of_processor_hartid(n);
 	cpuid = riscv_hartid_to_cpuid(hartid);
@@ -125,8 +124,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 		return 0;
 
 	/* This should be called only for boot cpu */
-	cs = per_cpu_ptr(&riscv_clocksource, cpuid);
-	clocksource_register_hz(cs, riscv_timebase);
+	clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 
 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
 			 "clockevents/riscv/timer:starting",
-- 
2.7.4

  parent reply	other threads:[~2018-12-13 23:14 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-13 23:14 [PATCH v2 0/4] Timer code cleanup Atish Patra
2018-12-13 23:14 ` [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
2018-12-14  9:17   ` Daniel Lezcano
2019-01-04  0:36     ` Palmer Dabbelt
2019-01-07  8:56       ` Daniel Lezcano
2018-12-13 23:14 ` [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
2018-12-14  9:24   ` Daniel Lezcano
2018-12-13 23:14 ` Atish Patra [this message]
2018-12-13 23:14 ` [PATCH v2 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Atish Patra

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