From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>,
Simon Horman <horms@verge.net.au>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Mark Rutland <mark.rutland@arm.com>
Cc: Fabrizio Castro <fabrizio.castro@bp.renesas.com>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>
Subject: [PATCH 6/9] arm64: dts: renesas: r8a774c0: Add GPIO device nodes
Date: Fri, 14 Dec 2018 09:10:10 +0000 [thread overview]
Message-ID: <1544778613-24279-7-git-send-email-fabrizio.castro@bp.renesas.com> (raw)
In-Reply-To: <1544778613-24279-1-git-send-email-fabrizio.castro@bp.renesas.com>
Add GPIO device nodes to the DT of the r8a774c0 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 105 ++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index afb4751..f09a240 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -105,6 +105,111 @@
#size-cells = <2>;
ranges;
+ gpio0: gpio@e6050000 {
+ compatible = "renesas,gpio-r8a774c0",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 18>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio@e6051000 {
+ compatible = "renesas,gpio-r8a774c0",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 23>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio@e6052000 {
+ compatible = "renesas,gpio-r8a774c0",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio@e6053000 {
+ compatible = "renesas,gpio-r8a774c0",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 16>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio@e6054000 {
+ compatible = "renesas,gpio-r8a774c0",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 11>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio@e6055000 {
+ compatible = "renesas,gpio-r8a774c0",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio@e6055400 {
+ compatible = "renesas,gpio-r8a774c0",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 18>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 906>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 906>;
+ };
+
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a774c0";
reg = <0 0xe6060000 0 0x508>;
--
2.7.4
next prev parent reply other threads:[~2018-12-14 9:10 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-14 9:10 [PATCH 0/9] RZ/G2E basic device tree Fabrizio Castro
2018-12-14 9:10 ` [PATCH 1/9] arm64: dts: renesas: Initial device tree for r8a774c0 Fabrizio Castro
2018-12-17 16:04 ` Geert Uytterhoeven
2018-12-14 9:10 ` [PATCH 2/9] arm64: dts: renesas: r8a774c0: Add SYS-DMAC controller nodes Fabrizio Castro
2018-12-17 16:04 ` Geert Uytterhoeven
2018-12-14 9:10 ` [PATCH 3/9] arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes Fabrizio Castro
2018-12-17 16:05 ` Geert Uytterhoeven
2018-12-14 9:10 ` [PATCH 4/9] arm64: dts: renesas: r8a774c0: Add INTC-EX device node Fabrizio Castro
2018-12-17 16:06 ` Geert Uytterhoeven
2018-12-14 9:10 ` [PATCH 5/9] arm64: dts: renesas: r8a774c0: Add PFC support Fabrizio Castro
2018-12-17 16:06 ` Geert Uytterhoeven
2018-12-14 9:10 ` Fabrizio Castro [this message]
2018-12-17 16:06 ` [PATCH 6/9] arm64: dts: renesas: r8a774c0: Add GPIO device nodes Geert Uytterhoeven
2018-12-14 9:10 ` [PATCH 7/9] arm64: dts: renesas: r8a774c0: Add Ethernet AVB node Fabrizio Castro
2018-12-17 16:07 ` Geert Uytterhoeven
2018-12-14 9:10 ` [PATCH 8/9] arm64: dts: renesas: r8a774c0: Add watchdog support Fabrizio Castro
2018-12-17 16:07 ` Geert Uytterhoeven
2018-12-14 9:10 ` [PATCH 9/9] arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core Fabrizio Castro
2018-12-17 16:08 ` Geert Uytterhoeven
2018-12-15 15:10 ` [PATCH 0/9] RZ/G2E basic device tree Simon Horman
2018-12-18 10:12 ` Simon Horman
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