From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: robh+dt@kernel.org, mark.rutland@arm.com, mperttunen@nvidia.com,
thierry.reding@gmail.com, jonathanh@nvidia.com,
adrian.hunter@intel.com, ulf.hansson@linaro.org
Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org,
Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: [PATCH V5 1/3] mmc: sdhci: Fix sdhci_do_enable_v4_mode
Date: Thu, 20 Dec 2018 17:25:07 -0800 [thread overview]
Message-ID: <1545355509-6914-2-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1545355509-6914-1-git-send-email-skomatineni@nvidia.com>
V4_MODE is Bit-15 of SDHCI_HOST_CONTROL2 register.
Need to perform word access to this register.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/sdhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 99bdae53fa2e..fde984d10619 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -127,12 +127,12 @@ static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
{
u16 ctrl2;
- ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2);
+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
if (ctrl2 & SDHCI_CTRL_V4_MODE)
return;
ctrl2 |= SDHCI_CTRL_V4_MODE;
- sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL);
+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
}
/*
--
2.7.4
next prev parent reply other threads:[~2018-12-21 1:25 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-21 1:25 [PATCH V5 0/3] HW Command Queue support for Tegra SDMMC Sowjanya Komatineni
2018-12-21 1:25 ` Sowjanya Komatineni [this message]
2018-12-27 8:13 ` [PATCH V5 1/3] mmc: sdhci: Fix sdhci_do_enable_v4_mode Adrian Hunter
2018-12-21 1:25 ` [PATCH V5 2/3] arm64: dtsi: Fix SDMMC address range Sowjanya Komatineni
2018-12-21 1:25 ` [PATCH V5 3/3] mmc: tegra: HW Command Queue Support for Tegra SDMMC Sowjanya Komatineni
2018-12-27 9:05 ` Adrian Hunter
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