From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yong Wu Subject: Re: [PATCH v4 10/18] iommu/mediatek: Add mt8183 IOMMU support Date: Sat, 22 Dec 2018 11:58:03 +0800 Message-ID: <1545451083.29587.91.camel@mhfsdcap03> References: <1544258371-4600-1-git-send-email-yong.wu@mediatek.com> <1544258371-4600-11-git-send-email-yong.wu@mediatek.com> <07f6276d-e7b5-ef82-9c38-1fa0af0cd9f3@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <07f6276d-e7b5-ef82-9c38-1fa0af0cd9f3-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Matthias Brugger Cc: youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Nicolas Boichat , arnd-r2nGTMty4D4@public.gmane.org, srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, Will Deacon , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Tomasz Figa , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Rob Herring , linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Arvind Yadav , yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, Robin Murphy , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Fri, 2018-12-21 at 19:31 +0100, Matthias Brugger wrote: > > On 08/12/2018 09:39, Yong Wu wrote: > > The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use > > the ARM Short-descriptor like mt8173, and most of the HW registers > > are the same. > > > > Here list main differences between mt8183 and mt8173/mt2712: > > 1) mt8183 has only one M4U HW like mt8173 while mt2712 has two. > > 2) mt8183 don't have the "bclk" clock, it use the EMI clock instead. > > 3) mt8183 can support the dram over 4GB, but it doesn't call this "4GB > > mode". > > 4) mt8183 pgtable base register(0x0) extend bit[1:0] which represent > > the bit[33:32] in the physical address of the pgtable base, But the > > standard ttbr0[1] means the S bit which is enabled defaultly, Hence, > > we add a mask. > > 5) mt8183 HW has a GALS modules, SMI should enable "has_gals" support. > > 6) the larb-id in smi-common is remapped. M4U should enable > > larbid_remapped support. > > > > Signed-off-by: Yong Wu > > --- [...] > > +static const struct mtk_iommu_plat_data mt8183_data = { > > + .m4u_plat = M4U_MT8183, > > + .larbid_remap_enable = true, > > + .larbid_remapped = {0, 4, 5, 6, 7, 2, 3, 1}, > > Aren't we reinventing the wheel here? > Why can't we use larb-id to get the correct id insteaf of providing another data > structure for the remapping? Sorry, The remapping id is arbitrary, there is no rule to get it from the larb-id. >>From Nicolas's comment, I plan to delete "larbid_remap_enable" and only use "larbid_remap". The other SoCs use the linear mapping here. In addition, I have to apologize that here will may be improved for mt2712. There are 2 smi-common(smi-common0 and smi-common1) in mt2712, actually the remapping relationship for smi-common1 is also different. If it is really needed, I plan to change it from "larbid_remap" to "larbid_remap[2]" which 0 is for smi-common0 and 1 is for smi-common1. Of course, it doesn't affect the iommu functions and only prints the error log when IOMMU translation fault. > > Regards, > Matthias [...]