From: Roger Quadros <rogerq@ti.com>
To: t-kristo@ti.com
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Roger Quadros <rogerq@ti.com>, Nishanth Menon <nm@ti.com>,
Lokesh Vutla <lokeshvutla@ti.com>,
"Andrew F . Davis" <afd@ti.com>
Subject: [PATCH] arm64: dts: ti: k3-am65: Add MSMC RAM node
Date: Fri, 11 Jan 2019 11:44:15 +0200 [thread overview]
Message-ID: <1547199855-16374-1-git-send-email-rogerq@ti.com> (raw)
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram
node so drivers can use it via genpool API.
Following areas are marked reserved:
- Lower 128KB for ATF
- 64KB@0xf0000 for SYSFW
- Upper 1MB for cache
The reserved locations are subject to change at runtime by
the bootloader.
Cc: Nishanth Menon <nm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Andrew F. Davis <afd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 272cf8f..5a18150 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -6,6 +6,26 @@
*/
&cbass_main {
+ msmc_ram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x70000000 0x0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x70000000 0x200000>;
+
+ atf-sram@0 {
+ reg = <0x0 0x20000>;
+ };
+
+ sysfw-sram@f0000 {
+ reg = <0xf0000 0x10000>;
+ };
+
+ l3cache-sram@100000 {
+ reg = <0x100000 0x100000>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
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next reply other threads:[~2019-01-11 9:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-11 9:44 Roger Quadros [this message]
2019-02-05 12:25 ` [PATCH] arm64: dts: ti: k3-am65: Add MSMC RAM node Roger Quadros
2019-02-15 8:46 ` Tero Kristo
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