[PATCH 1/2] Documentation: usb: dwc3: add power down clock scale property

[PATCH 1/2] Documentation: usb: dwc3: add power down clock scale property

[Jun Li]

The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock
source to a small part of the USB3 core that operates when the
SS PHY is in its lowest power(P3) state, and therefore does
not provide a clock. The power down scale specifies how many
suspend_clk periods fit into a 16 KHz clock period, details
can see DWC3 databook register GCTL.PWRDNSCALE.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 Documentation/devicetree/bindings/usb/dwc3.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 3e4c38b..d1c8b62 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -102,6 +102,12 @@ Optional properties:
 			more than one value, which means undefined length INCR burst type
 			enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
 
+ - snps,power-down-scale: Power down scale field specifies how many suspend_clk
+			periods fit into a 16 Khz clock period. When performing
+			the division, round up the remainder. Suspend clock is
+			from 32kHz to 125MHz, means the value range is 2~8000.
+			(details see DWC_usb3 databook register GCTL.PWRDNSCALE).
+
  - in addition all properties from usb-xhci.txt from the current directory are
    supported as well
 
-- 
2.7.4

[PATCH 2/2] dwc3: add power down clock scale setting when init core

[Jun Li]

Set the right power down clock scale if the property
"snps,power-down-scale" is specified.

Signed-off-by: Li Jun <jun.li@nxp.com>
---
 drivers/usb/dwc3/core.c | 15 +++++++++++++++
 drivers/usb/dwc3/core.h |  1 +
 2 files changed, 16 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 88c80fc..c41c0b2 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -878,6 +878,19 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 }
 
+static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
+{
+	u32 reg, scale;
+
+	if (!device_property_read_u32(dwc->dev, "snps,power-down-scale",
+				      &scale)) {
+		reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+		reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
+		reg |= DWC3_GCTL_PWRDNSCALE(scale);
+		dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+	}
+}
+
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -908,6 +921,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 			dwc->maximum_speed = USB_SPEED_HIGH;
 	}
 
+	dwc3_set_power_down_clk_scale(dwc);
+
 	ret = dwc3_phy_setup(dwc);
 	if (ret)
 		goto err0;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5bfb625..8cdaab3 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -216,6 +216,7 @@
 
 /* Global Configuration Register */
 #define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)
+#define DWC3_GCTL_PWRDNSCALE_MASK	DWC3_GCTL_PWRDNSCALE(0x1fff)
 #define DWC3_GCTL_U2RSTECN	BIT(16)
 #define DWC3_GCTL_RAMCLKSEL(x)	(((x) & DWC3_GCTL_CLK_MASK) << 6)
 #define DWC3_GCTL_CLK_BUS	(0)
-- 
2.7.4

Re: [PATCH 1/2] Documentation: usb: dwc3: add power down clock scale property

[Rob Herring]

On Tue, Jan 22, 2019 at 10:37:17AM +0000, Jun Li wrote:
> The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock
> source to a small part of the USB3 core that operates when the
> SS PHY is in its lowest power(P3) state, and therefore does
> not provide a clock. The power down scale specifies how many
> suspend_clk periods fit into a 16 KHz clock period, details
> can see DWC3 databook register GCTL.PWRDNSCALE.
> 
> Signed-off-by: Li Jun <jun.li@nxp.com>
> ---
>  Documentation/devicetree/bindings/usb/dwc3.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 3e4c38b..d1c8b62 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -102,6 +102,12 @@ Optional properties:
>  			more than one value, which means undefined length INCR burst type
>  			enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
>  
> + - snps,power-down-scale: Power down scale field specifies how many suspend_clk
> +			periods fit into a 16 Khz clock period. When performing
> +			the division, round up the remainder. Suspend clock is
> +			from 32kHz to 125MHz, means the value range is 2~8000.
> +			(details see DWC_usb3 databook register GCTL.PWRDNSCALE).
> +

Sounds like the suspend_clk should be provided as a clock input so you 
can calculate this value.

>   - in addition all properties from usb-xhci.txt from the current directory are
>     supported as well
>  
> -- 
> 2.7.4
> 

RE: [PATCH 1/2] Documentation: usb: dwc3: add power down clock scale property

[Jun Li]

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2019年2月23日 8:33
> To: Jun Li <jun.li@nxp.com>
> Cc: mark.rutland@arm.com; balbi@kernel.org; linux-usb@vger.kernel.org;
> devicetree@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH 1/2] Documentation: usb: dwc3: add power down clock scale
> property
> 
> On Tue, Jan 22, 2019 at 10:37:17AM +0000, Jun Li wrote:
> > The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to
> > a small part of the USB3 core that operates when the SS PHY is in its
> > lowest power(P3) state, and therefore does not provide a clock. The
> > power down scale specifies how many suspend_clk periods fit into a 16
> > KHz clock period, details can see DWC3 databook register
> > GCTL.PWRDNSCALE.
> >
> > Signed-off-by: Li Jun <jun.li@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/usb/dwc3.txt | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > index 3e4c38b..d1c8b62 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > @@ -102,6 +102,12 @@ Optional properties:
> >  			more than one value, which means undefined length INCR burst type
> >  			enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
> >
> > + - snps,power-down-scale: Power down scale field specifies how many
> suspend_clk
> > +			periods fit into a 16 Khz clock period. When performing
> > +			the division, round up the remainder. Suspend clock is
> > +			from 32kHz to 125MHz, means the value range is 2~8000.
> > +			(details see DWC_usb3 databook register GCTL.PWRDNSCALE).
> > +
> 
> Sounds like the suspend_clk should be provided as a clock input so you can
> calculate this value.

Yes, I will go this approach by update dts with suspend_clk of dwc3

Thanks
Li Jun 
> 
> >   - in addition all properties from usb-xhci.txt from the current directory are
> >     supported as well
> >
> > --
> > 2.7.4
> >