From: <shun-chih.yu@mediatek.com>
To: Sean Wang <sean.wang@mediatek.com>, Vinod Koul <vkoul@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
srv_wsdupstream@mediatek.com, linux-mediatek@lists.infradead.org,
dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5] add support for Mediatek Command-Queue DMA controller on MT6765 SoC
Date: Thu, 24 Jan 2019 15:14:18 +0800 [thread overview]
Message-ID: <1548314060-4833-1-git-send-email-shun-chih.yu@mediatek.com> (raw)
This patchset introduces support for MediaTek Command-Queue DMA controller.
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated to memory-to-memory transfer through queue-based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is extended to support 32 virtual channels for multiple dma users to issue dma requests onto the CQDMA simultaneously.
dmatest result:
dmatest: dma0chan0-copy2: summary 5000 tests, 0 failures 3500 iops 28037 KB/s (0)
dmatest: dma0chan0-copy4: summary 5000 tests, 0 failures 3494 iops 27612 KB/s (0)
dmatest: dma0chan0-copy1: summary 5000 tests, 0 failures 3491 iops 27749 KB/s (0)
dmatest: dma0chan0-copy7: summary 5000 tests, 0 failures 3673 iops 29092 KB/s (0)
dmatest: dma0chan0-copy6: summary 5000 tests, 0 failures 3763 iops 30237 KB/s (0)
dmatest: dma0chan0-copy0: summary 5000 tests, 0 failures 3730 iops 30131 KB/s (0)
dmatest: dma0chan0-copy3: summary 5000 tests, 0 failures 3717 iops 29569 KB/s (0)
dmatest: dma0chan0-copy5: summary 5000 tests, 0 failures 3699 iops 29302 KB/s (0)
Changes since v4:
- remove redundant queue structure in mtk_cqdma_pchan
- remove redundant completion management
- fix wrong residue assignment in mtk_cqdma_tx_status
- fix typos
Changes since v3:
- simplify the ISR and management on descriptors by removing tasklet and ASYNC_TX_ENABLE_CHANNEL_SWITCH
- remove useless field in mtk_cqdma_vdesc structure
- change dev_info to dev_dbg
- fix typos
Changes since v2:
- fix build warning for kernel with DMA address in 32-bit
Changes since v1:
- remove unused macros, typos
- leverage ASYNC_TX_ENABLE_CHANNEL_SWITCH to maintain DMA descriptor list
Shun-Chih Yu (2):
dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller
bindings
dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for
MT6765 SoC
.../devicetree/bindings/dma/mtk-cqdma.txt | 31 +
drivers/dma/mediatek/Kconfig | 12 +
drivers/dma/mediatek/Makefile | 1 +
drivers/dma/mediatek/mtk-cqdma.c | 748 ++++++++++++++++++++
4 files changed, 792 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
next reply other threads:[~2019-01-24 7:14 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-24 7:14 shun-chih.yu [this message]
2019-01-24 7:14 ` [PATCH v5 1/2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings shun-chih.yu
2019-01-24 7:14 ` [PATCH v5 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC shun-chih.yu
2019-01-24 9:35 ` [PATCH v5] add support for Mediatek Command-Queue DMA controller on " Sean Wang
2019-01-24 10:16 ` Shun-Chih.Yu
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