* [PATCH] arm64: dts: imx8mq: Add QuadSPI controller
@ 2019-01-29 16:34 Carlo Caione
2019-01-29 16:42 ` Lucas Stach
0 siblings, 1 reply; 4+ messages in thread
From: Carlo Caione @ 2019-01-29 16:34 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
linux-imx, l.stach, devicetree, linux-arm-kernel
Cc: Carlo Caione
Add a node for the Freescale/NXP QuadSPI controller with a proper
pinctrl set and enable it for the i.MX8MQ EVK board.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 27 ++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 ++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index f74b13aa5aa5..ae181c2a5003 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -137,6 +137,21 @@
status = "okay";
};
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash0: n25q256a@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,n25q256a", "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ spi-nor,ddr-quad-read-dummy = <6>;
+ };
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -195,6 +210,18 @@
>;
};
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
+ MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+
+ >;
+ };
+
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index dbedc4a5e7fb..e0059f451591 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -516,6 +516,19 @@
};
};
+ spi0: spi@30bb0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-qspi";
+ reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
+ <&clk IMX8MQ_CLK_QSPI_ROOT>;
+ clock-names = "qspi_en", "qspi";
+ status = "disabled";
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
--
2.19.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: dts: imx8mq: Add QuadSPI controller
2019-01-29 16:34 [PATCH] arm64: dts: imx8mq: Add QuadSPI controller Carlo Caione
@ 2019-01-29 16:42 ` Lucas Stach
2019-01-29 16:54 ` Carlo Caione
0 siblings, 1 reply; 4+ messages in thread
From: Lucas Stach @ 2019-01-29 16:42 UTC (permalink / raw)
To: Carlo Caione, robh+dt, mark.rutland, shawnguo, s.hauer, kernel,
festevam, linux-imx, devicetree, linux-arm-kernel
Hi Carlo,
Am Dienstag, den 29.01.2019, 16:34 +0000 schrieb Carlo Caione:
> Add a node for the Freescale/NXP QuadSPI controller with a proper
> pinctrl set and enable it for the i.MX8MQ EVK board.
>
> > Signed-off-by: Carlo Caione <ccaione@baylibre.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 27 ++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 ++++++++++
> 2 files changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index f74b13aa5aa5..ae181c2a5003 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -137,6 +137,21 @@
> > status = "okay";
> };
>
> +&spi0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_qspi>;
> > + status = "okay";
> +
> > > + flash0: n25q256a@0 {
> > + reg = <0>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "micron,n25q256a", "jedec,spi-nor";
> > + spi-max-frequency = <29000000>;
> > + spi-nor,ddr-quad-read-dummy = <6>;
> > + };
> +};
> +
> &usdhc1 {
> > pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > pinctrl-0 = <&pinctrl_usdhc1>;
> @@ -195,6 +210,18 @@
> > >;
> > };
>
> > + pinctrl_qspi: qspigrp {
> > + fsl,pins = <
> > > + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
> > > + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
> > > + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
> > > + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
> > > + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
> > > + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
> +
> > + >;
> > + };
> +
> > pinctrl_reg_usdhc2: regusdhc2grpgpio {
> > fsl,pins = <
> > > MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index dbedc4a5e7fb..e0059f451591 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -516,6 +516,19 @@
> > };
> > };
>
> + spi0: spi@30bb0000 {
30bb0000 is part of the AIPS3 bus address space, so please move this to
the correct location within this bus node.
> + #address-cells = <1>;
> > + #size-cells = <0>;
> + compatible = "fsl,imx7d-qspi";
Please add a "fsl,imx8mq-qspi" compatible here, as was done with all
the other nodes in this file, so we can match this in the driver should
the need arise.
> + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>;
> > + reg-names = "QuadSPI", "QuadSPI-memory";
> > + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
> + <&clk IMX8MQ_CLK_QSPI_ROOT>;
Please align the second clock reference, as is done for all other
peripheral nodes in this file.
Regards,
Lucas
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: dts: imx8mq: Add QuadSPI controller
2019-01-29 16:42 ` Lucas Stach
@ 2019-01-29 16:54 ` Carlo Caione
2019-01-29 17:40 ` Lucas Stach
0 siblings, 1 reply; 4+ messages in thread
From: Carlo Caione @ 2019-01-29 16:54 UTC (permalink / raw)
To: Lucas Stach, robh+dt, mark.rutland, shawnguo, s.hauer, kernel,
festevam, linux-imx, devicetree, linux-arm-kernel
On 29/01/2019 16:42, Lucas Stach wrote:
> Hi Carlo,
Hi Lucas,
>> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> @@ -516,6 +516,19 @@
>>> };
>>> };
>>
>> + spi0: spi@30bb0000 {
>
> 30bb0000 is part of the AIPS3 bus address space, so please move this to
> the correct location within this bus node.
The problem is that the "QuadSPI-memory" region doesn't fall within the
memory range of the AIPS3 bus, so the devm_ioremap_resource is failing
when moving the node there.
>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>> + compatible = "fsl,imx7d-qspi";
>
> Please add a "fsl,imx8mq-qspi" compatible here, as was done with all
> the other nodes in this file, so we can match this in the driver should
> the need arise.
This is odd since at least for the AmLogic SoCs we are going exactly in
the opposite direction where we avoid to add unnecessary compatibles if
that's not strictly required.
>> + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>;
>>> + reg-names = "QuadSPI", "QuadSPI-memory";
>>> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
>> + <&clk IMX8MQ_CLK_QSPI_ROOT>;
>
> Please align the second clock reference, as is done for all other
> peripheral nodes in this file.
I'll do.
Cheers,
--
Carlo Caione
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: dts: imx8mq: Add QuadSPI controller
2019-01-29 16:54 ` Carlo Caione
@ 2019-01-29 17:40 ` Lucas Stach
0 siblings, 0 replies; 4+ messages in thread
From: Lucas Stach @ 2019-01-29 17:40 UTC (permalink / raw)
To: Carlo Caione, robh+dt, mark.rutland, shawnguo, s.hauer, kernel,
festevam, linux-imx, devicetree, linux-arm-kernel
Am Dienstag, den 29.01.2019, 16:54 +0000 schrieb Carlo Caione:
> On 29/01/2019 16:42, Lucas Stach wrote:
> > Hi Carlo,
>
> Hi Lucas,
>
> > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > > @@ -516,6 +516,19 @@
> > > > > > > > };
> > > > };
> > >
> > >
> > > + spi0: spi@30bb0000 {
> >
> > 30bb0000 is part of the AIPS3 bus address space, so please move this to
> > the correct location within this bus node.
>
> The problem is that the "QuadSPI-memory" region doesn't fall within the
> memory range of the AIPS3 bus, so the devm_ioremap_resource is failing
> when moving the node there.
Uh, that's interesting. Normally the DTs are organized along the
control path and I guess the QuadSPI-memory is not really a control
path, but the fast memory access path. Maybe this is something the DT
folks could take a look at.
But then I would still prefer to have the QSPI controller moved into
the correct control bus. I guess we can work around your
devm_ioremap_resource failing issue by adding the QSPI-memory region to
the AIPS3 bus ranges.
> > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > >
> > > + compatible = "fsl,imx7d-qspi";
> >
> > Please add a "fsl,imx8mq-qspi" compatible here, as was done with all
> > the other nodes in this file, so we can match this in the driver should
> > the need arise.
>
> This is odd since at least for the AmLogic SoCs we are going exactly in
> the opposite direction where we avoid to add unnecessary compatibles if
> that's not strictly required.
It's a safety net, so we don't need to change existing DTBs if it turns
out that a specific SoC integration has a bug that needs a workaround
in the driver.
This is one of things I've proposed in my ELC-E talk "Stable Devicetree
ABI: it's possible!", which was generally well received by the DT
folks.
Regards,
Lucas
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-01-29 16:34 [PATCH] arm64: dts: imx8mq: Add QuadSPI controller Carlo Caione
2019-01-29 16:42 ` Lucas Stach
2019-01-29 16:54 ` Carlo Caione
2019-01-29 17:40 ` Lucas Stach
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