* [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores
2019-02-15 18:07 [PATCH v2 0/3] arm: dts: imx8mq: Add cpufreq support Abel Vesa
@ 2019-02-15 18:07 ` Abel Vesa
2019-02-15 18:07 ` [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator Abel Vesa
2019-02-15 18:07 ` [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Abel Vesa
2 siblings, 0 replies; 8+ messages in thread
From: Abel Vesa @ 2019-02-15 18:07 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer, Lucas Stach,
Angus Ainslie
Cc: Fabio Estevam, Anson Huang, devicetree@vger.kernel.org,
dl-linux-imx, Linux Kernel Mailing List,
linux-arm-kernel@lists.infradead.org, Abel Vesa
The clocks and their latencies will be used by cpufreq-dt.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4..1a89062 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -87,6 +87,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
@@ -95,6 +97,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
@@ -103,6 +107,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
@@ -111,6 +117,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator
2019-02-15 18:07 [PATCH v2 0/3] arm: dts: imx8mq: Add cpufreq support Abel Vesa
2019-02-15 18:07 ` [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Abel Vesa
@ 2019-02-15 18:07 ` Abel Vesa
2019-02-28 14:15 ` Shawn Guo
2019-02-15 18:07 ` [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Abel Vesa
2 siblings, 1 reply; 8+ messages in thread
From: Abel Vesa @ 2019-02-15 18:07 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer, Lucas Stach,
Angus Ainslie
Cc: Fabio Estevam, Anson Huang, devicetree@vger.kernel.org,
dl-linux-imx, Linux Kernel Mailing List,
linux-arm-kernel@lists.infradead.org, Abel Vesa
According to the schematics, this is a MP2147 switch converter
which is controlled by GPIO1_IO13. When set the gpio is set to
high the regulator output is set to 0.9V. When the gpio is set
to low the regulator output is set to 1V.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 36 ++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 54737bf..e5da3dd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -31,6 +31,35 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ buck2_reg: buck2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_buck2>;
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ states = <1000000 0x0
+ 900000 0x1>;
+ enable-active-high;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
};
&fec1 {
@@ -203,6 +232,13 @@
};
&iomuxc {
+ pinctrl_buck2: vddarmgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
+ >;
+
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator
2019-02-15 18:07 ` [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator Abel Vesa
@ 2019-02-28 14:15 ` Shawn Guo
2019-02-28 14:29 ` Abel Vesa
0 siblings, 1 reply; 8+ messages in thread
From: Shawn Guo @ 2019-02-28 14:15 UTC (permalink / raw)
To: Abel Vesa
Cc: Rob Herring, Mark Rutland, Sascha Hauer, Lucas Stach,
Angus Ainslie, devicetree@vger.kernel.org, Anson Huang,
Linux Kernel Mailing List, dl-linux-imx, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
On Fri, Feb 15, 2019 at 06:07:23PM +0000, Abel Vesa wrote:
> According to the schematics, this is a MP2147 switch converter
> which is controlled by GPIO1_IO13. When set the gpio is set to
> high the regulator output is set to 0.9V. When the gpio is set
> to low the regulator output is set to 1V.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 36 ++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index 54737bf..e5da3dd 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -31,6 +31,35 @@
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + buck2_reg: buck2 {
Please follow regulator-xxx naming convention.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_buck2>;
> + compatible = "regulator-gpio";
> + regulator-name = "vdd_arm";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1000000>;
> + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
> + states = <1000000 0x0
> + 900000 0x1>;
> + enable-active-high;
The property only makes sense when enable-gpio is present?
Shawn
> + };
> +};
> +
> +&A53_0 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_1 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_2 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&A53_3 {
> + cpu-supply = <&buck2_reg>;
> };
>
> &fec1 {
> @@ -203,6 +232,13 @@
> };
>
> &iomuxc {
> + pinctrl_buck2: vddarmgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
> + >;
> +
> + };
> +
> pinctrl_fec1: fec1grp {
> fsl,pins = <
> MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator
2019-02-28 14:15 ` Shawn Guo
@ 2019-02-28 14:29 ` Abel Vesa
0 siblings, 0 replies; 8+ messages in thread
From: Abel Vesa @ 2019-02-28 14:29 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Sascha Hauer, Lucas Stach,
Angus Ainslie, devicetree@vger.kernel.org, Anson Huang,
Linux Kernel Mailing List, dl-linux-imx, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
On 19-02-28 22:15:46, Shawn Guo wrote:
> On Fri, Feb 15, 2019 at 06:07:23PM +0000, Abel Vesa wrote:
> > According to the schematics, this is a MP2147 switch converter
> > which is controlled by GPIO1_IO13. When set the gpio is set to
> > high the regulator output is set to 0.9V. When the gpio is set
> > to low the regulator output is set to 1V.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 36 ++++++++++++++++++++++++++++
> > 1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > index 54737bf..e5da3dd 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > @@ -31,6 +31,35 @@
> > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > enable-active-high;
> > };
> > +
> > + buck2_reg: buck2 {
>
> Please follow regulator-xxx naming convention.
>
Will do.
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_buck2>;
> > + compatible = "regulator-gpio";
> > + regulator-name = "vdd_arm";
> > + regulator-min-microvolt = <900000>;
> > + regulator-max-microvolt = <1000000>;
> > + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
> > + states = <1000000 0x0
> > + 900000 0x1>;
> > + enable-active-high;
>
> The property only makes sense when enable-gpio is present?
>
Will remove it.
> Shawn
>
> > + };
> > +};
> > +
> > +&A53_0 {
> > + cpu-supply = <&buck2_reg>;
> > +};
> > +
> > +&A53_1 {
> > + cpu-supply = <&buck2_reg>;
> > +};
> > +
> > +&A53_2 {
> > + cpu-supply = <&buck2_reg>;
> > +};
> > +
> > +&A53_3 {
> > + cpu-supply = <&buck2_reg>;
> > };
> >
> > &fec1 {
> > @@ -203,6 +232,13 @@
> > };
> >
> > &iomuxc {
> > + pinctrl_buck2: vddarmgrp {
> > + fsl,pins = <
> > + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
> > + >;
> > +
> > + };
> > +
> > pinctrl_fec1: fec1grp {
> > fsl,pins = <
> > MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> > --
> > 2.7.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=02%7C01%7Cabel.vesa%40nxp.com%7C7f571130a0114fb84fe408d69d87606f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636869602101094479&sdata=vsNlfbgqglUuVsFyULjTMm5Hqwd6chpsVa0V05ugDG0%3D&reserved=0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties
2019-02-15 18:07 [PATCH v2 0/3] arm: dts: imx8mq: Add cpufreq support Abel Vesa
2019-02-15 18:07 ` [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Abel Vesa
2019-02-15 18:07 ` [PATCH v2 2/3] arm64: dts: imx8mq: Add the buck vdd_arm regulator Abel Vesa
@ 2019-02-15 18:07 ` Abel Vesa
2019-02-28 14:20 ` Shawn Guo
2 siblings, 1 reply; 8+ messages in thread
From: Abel Vesa @ 2019-02-15 18:07 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Shawn Guo, Sascha Hauer, Lucas Stach,
Angus Ainslie
Cc: Fabio Estevam, Anson Huang, devicetree@vger.kernel.org,
dl-linux-imx, Linux Kernel Mailing List,
linux-arm-kernel@lists.infradead.org, Abel Vesa
Add the 0.8GHz and 1GHz opps. According to the datasheet:
https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf
section 3.1.3 Operating ranges.
The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V.
The 1GHz runs in overdrive mode with the regulator set to 1V.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 1a89062..ebdec9e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -91,6 +91,7 @@
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_0_opp_table>;
};
A53_1: cpu@1 {
@@ -101,6 +102,7 @@
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_0_opp_table>;
};
A53_2: cpu@2 {
@@ -111,6 +113,7 @@
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_0_opp_table>;
};
A53_3: cpu@3 {
@@ -121,6 +124,7 @@
clocks = <&clk IMX8MQ_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_0_opp_table>;
};
A53_L2: l2-cache0 {
@@ -666,6 +670,25 @@
status = "disabled";
};
+
+ a53_0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <150000>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties
2019-02-15 18:07 ` [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Abel Vesa
@ 2019-02-28 14:20 ` Shawn Guo
2019-02-28 14:28 ` Abel Vesa
0 siblings, 1 reply; 8+ messages in thread
From: Shawn Guo @ 2019-02-28 14:20 UTC (permalink / raw)
To: Abel Vesa
Cc: Rob Herring, Mark Rutland, Sascha Hauer, Lucas Stach,
Angus Ainslie, devicetree@vger.kernel.org, Anson Huang,
Linux Kernel Mailing List, dl-linux-imx, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
On Fri, Feb 15, 2019 at 06:07:24PM +0000, Abel Vesa wrote:
> Add the 0.8GHz and 1GHz opps. According to the datasheet:
> https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf
> section 3.1.3 Operating ranges.
>
> The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V.
> The 1GHz runs in overdrive mode with the regulator set to 1V.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 1a89062..ebdec9e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -91,6 +91,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_1: cpu@1 {
> @@ -101,6 +102,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_2: cpu@2 {
> @@ -111,6 +113,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_3: cpu@3 {
> @@ -121,6 +124,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_L2: l2-cache0 {
> @@ -666,6 +670,25 @@
> status = "disabled";
> };
>
> +
> + a53_0_opp_table: opp-table {
What's the point of having '0' in the label name, considering it's
actually referred by all CPU nodes?
Shawn
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <150000>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <150000>;
> + opp-suspend;
> + };
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>, /* GIC Dist */
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties
2019-02-28 14:20 ` Shawn Guo
@ 2019-02-28 14:28 ` Abel Vesa
0 siblings, 0 replies; 8+ messages in thread
From: Abel Vesa @ 2019-02-28 14:28 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, Sascha Hauer, Lucas Stach,
Angus Ainslie, devicetree@vger.kernel.org, Anson Huang,
Linux Kernel Mailing List, dl-linux-imx, Fabio Estevam,
linux-arm-kernel@lists.infradead.org
On 19-02-28 22:20:32, Shawn Guo wrote:
> On Fri, Feb 15, 2019 at 06:07:24PM +0000, Abel Vesa wrote:
> > Add the 0.8GHz and 1GHz opps. According to the datasheet:
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fdata-sheet%2FIMX8MDQLQIEC.pdf&data=02%7C01%7Cabel.vesa%40nxp.com%7C05d898b625824204bb3908d69d880aaf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636869604952370425&sdata=yDuM%2ByO%2F9twQ3cXTR%2FkCSSfxOMm015qG%2FfBSFZC91SQ%3D&reserved=0
> > section 3.1.3 Operating ranges.
> >
> > The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V.
> > The 1GHz runs in overdrive mode with the regulator set to 1V.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 1a89062..ebdec9e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -91,6 +91,7 @@
> > clocks = <&clk IMX8MQ_CLK_ARM>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + operating-points-v2 = <&a53_0_opp_table>;
> > };
> >
> > A53_1: cpu@1 {
> > @@ -101,6 +102,7 @@
> > clocks = <&clk IMX8MQ_CLK_ARM>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + operating-points-v2 = <&a53_0_opp_table>;
> > };
> >
> > A53_2: cpu@2 {
> > @@ -111,6 +113,7 @@
> > clocks = <&clk IMX8MQ_CLK_ARM>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + operating-points-v2 = <&a53_0_opp_table>;
> > };
> >
> > A53_3: cpu@3 {
> > @@ -121,6 +124,7 @@
> > clocks = <&clk IMX8MQ_CLK_ARM>;
> > enable-method = "psci";
> > next-level-cache = <&A53_L2>;
> > + operating-points-v2 = <&a53_0_opp_table>;
> > };
> >
> > A53_L2: l2-cache0 {
> > @@ -666,6 +670,25 @@
> > status = "disabled";
> > };
> >
> > +
> > + a53_0_opp_table: opp-table {
>
> What's the point of having '0' in the label name, considering it's
> actually referred by all CPU nodes?
>
Good catch. Will remove and resend.
Thanks.
> Shawn
>
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-800000000 {
> > + opp-hz = /bits/ 64 <800000000>;
> > + opp-microvolt = <900000>;
> > + clock-latency-ns = <150000>;
> > + };
> > +
> > + opp-1000000000 {
> > + opp-hz = /bits/ 64 <1000000000>;
> > + opp-microvolt = <1000000>;
> > + clock-latency-ns = <150000>;
> > + opp-suspend;
> > + };
> > + };
> > +
> > gic: interrupt-controller@38800000 {
> > compatible = "arm,gic-v3";
> > reg = <0x38800000 0x10000>, /* GIC Dist */
> > --
> > 2.7.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
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