From mboxrd@z Thu Jan 1 00:00:00 1970 From: Abel Vesa Subject: [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Date: Fri, 15 Feb 2019 18:07:22 +0000 Message-ID: <1550254032-16451-2-git-send-email-abel.vesa@nxp.com> References: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Lucas Stach , Angus Ainslie Cc: Fabio Estevam , Anson Huang , "devicetree@vger.kernel.org" , dl-linux-imx , Linux Kernel Mailing List , "linux-arm-kernel@lists.infradead.org" , Abel Vesa List-Id: devicetree@vger.kernel.org The clocks and their latencies will be used by cpufreq-dt. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mq.dtsi index 9155bd4..1a89062 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -87,6 +87,8 @@ device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; + clock-latency =3D <61036>; /* two CLK32 periods */ + clocks =3D <&clk IMX8MQ_CLK_ARM>; enable-method =3D "psci"; next-level-cache =3D <&A53_L2>; }; @@ -95,6 +97,8 @@ device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; + clock-latency =3D <61036>; /* two CLK32 periods */ + clocks =3D <&clk IMX8MQ_CLK_ARM>; enable-method =3D "psci"; next-level-cache =3D <&A53_L2>; }; @@ -103,6 +107,8 @@ device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; + clock-latency =3D <61036>; /* two CLK32 periods */ + clocks =3D <&clk IMX8MQ_CLK_ARM>; enable-method =3D "psci"; next-level-cache =3D <&A53_L2>; }; @@ -111,6 +117,8 @@ device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; + clock-latency =3D <61036>; /* two CLK32 periods */ + clocks =3D <&clk IMX8MQ_CLK_ARM>; enable-method =3D "psci"; next-level-cache =3D <&A53_L2>; }; --=20 2.7.4