From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anson Huang Subject: [PATCH V4 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel Date: Thu, 21 Feb 2019 09:19:34 +0000 Message-ID: <1550740354-2701-3-git-send-email-Anson.Huang@nxp.com> References: <1550740354-2701-1-git-send-email-Anson.Huang@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1550740354-2701-1-git-send-email-Anson.Huang@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "a.zummo@towertech.it" , "alexandre.belloni@bootlin.com" , Aisheng Dong , "ulf.hansson@linaro.org" , Daniel Baluta , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-rtc@vger.kernel.org" Cc: dl-linux-imx List-Id: devicetree@vger.kernel.org On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is used for this function, this patch adds support for it. Signed-off-by: Anson Huang --- Changes since V3: - rename "gi3" to "gip3"; - add alias for getting mu id by driver. --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index 4c3dd95..f0a9224 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -21,6 +21,7 @@ mmc1 =3D &usdhc2; mmc2 =3D &usdhc3; serial0 =3D &adma_lpuart0; + mu1 =3D &lsio_mu1; }; =20 cpus { @@ -87,7 +88,8 @@ scu { compatible =3D "fsl,imx-scu"; mbox-names =3D "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3"; + "rx0", "rx1", "rx2", "rx3", + "gip3"; mboxes =3D <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 @@ -95,7 +97,8 @@ &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 - &lsio_mu1 1 3>; + &lsio_mu1 1 3 + &lsio_mu1 3 3>; =20 clk: clock-controller { compatible =3D "fsl,imx8qxp-clk"; --=20 2.7.4