* [PATCH v2 01/12] of: Add bindings of thermtrip for Tegra soctherm
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 02/12] thermal: tegra: support hw and sw shutdown Wei Ni
` (11 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Add optional property "nvidia,thermtrips".
If present, these trips will be used as HW shutdown trips,
and critical trips will be used as SW shutdown trips.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
.../bindings/thermal/nvidia,tegra124-soctherm.txt | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
index b6c0ae53d4dc..ab66d6feab4b 100644
--- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
+++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
@@ -55,10 +55,21 @@ Required properties :
- #cooling-cells: Should be 1. This cooling device only support on/off state.
See ./thermal.txt for a description of this property.
+Optional properties:
+- nvidia,thermtrips : When present, this property specifies the temperature at
+ which the soctherm hardware will assert the thermal trigger signal to the
+ Power Management IC, which can be configured to reset or shutdown the device.
+ It is an array of pairs where each pair represents a tsensor id followed by a
+ temperature in milli Celcius. In the absence of this property the critical
+ trip point will be used for thermtrip temperature.
+
Note:
-- the "critical" type trip points will be set to SOC_THERM hardware as the
-shut down temperature. Once the temperature of this thermal zone is higher
-than it, the system will be shutdown or reset by hardware.
+- the "critical" type trip points will be used to set the temperature at which
+the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips"
+property is missing. When the thermtrips property is present, the breach of a
+critical trip point is reported back to the thermal framework to implement
+software shutdown.
+
- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
temperature. Once the the temperature of this thermal zone is higher
than it, it will trigger the HW throttle event.
@@ -79,6 +90,9 @@ Example :
#thermal-sensor-cells = <1>;
+ nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
+ TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
+
throttle-cfgs {
/*
* When the "heavy" cooling device triggered,
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 02/12] thermal: tegra: support hw and sw shutdown
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
2019-02-21 10:18 ` [PATCH v2 01/12] of: Add bindings of thermtrip " Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 03/12] arm64: dts: tegra210: set thermtrip Wei Ni
` (10 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Currently the critical trip points in thermal framework are the only
way to specify a temperature at which HW should shutdown. This is
insufficient for certain platforms which would want an orderly
software shutdown in addition to HW shutdown.
This change support to parse "nvidia, thermtrips" property,
it allows soctherm DT to specify thermtrip temperatures so that
critical trip points framework can be used for doing software
shutdown.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/soctherm.c | 99 ++++++++++++++++++++++++++-----
drivers/thermal/tegra/soctherm.h | 6 ++
drivers/thermal/tegra/tegra210-soctherm.c | 8 +++
3 files changed, 98 insertions(+), 15 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index 45b41b885f49..4bb6c097c028 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -446,6 +446,24 @@ find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name)
return NULL;
}
+static int tsensor_group_thermtrip_get(struct tegra_soctherm *ts, int id)
+{
+ int i, temp = min_low_temp;
+ struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
+
+ if (id >= TEGRA124_SOCTHERM_SENSOR_NUM)
+ return temp;
+
+ if (tt) {
+ for (i = 0; i < ts->soc->num_ttgs; i++) {
+ if (tt[i].id == id)
+ return tt[i].temp;
+ }
+ }
+
+ return temp;
+}
+
static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp)
{
struct tegra_thermctl_zone *zone = data;
@@ -464,7 +482,16 @@ static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp)
return ret;
if (type == THERMAL_TRIP_CRITICAL) {
- return thermtrip_program(dev, sg, temp);
+ /*
+ * If thermtrips property is set in DT,
+ * doesn't need to program critical type trip to HW,
+ * if not, program critical trip to HW.
+ */
+ if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id))
+ return thermtrip_program(dev, sg, temp);
+ else
+ return 0;
+
} else if (type == THERMAL_TRIP_HOT) {
int i;
@@ -523,7 +550,8 @@ static int get_hot_temp(struct thermal_zone_device *tz, int *trip, int *temp)
* @dev: struct device * of the SOC_THERM instance
*
* Configure the SOC_THERM HW trip points, setting "THERMTRIP"
- * "THROTTLE" trip points , using "critical" or "hot" type trip_temp
+ * "THROTTLE" trip points , using "thermtrips", "critical" or "hot"
+ * type trip_temp
* from thermal zone.
* After they have been configured, THERMTRIP or THROTTLE will take
* action when the configured SoC thermal sensor group reaches a
@@ -545,28 +573,23 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
{
struct tegra_soctherm *ts = dev_get_drvdata(dev);
struct soctherm_throt_cfg *stc;
- int i, trip, temperature;
- int ret;
+ int i, trip, temperature, ret;
- ret = tz->ops->get_crit_temp(tz, &temperature);
- if (ret) {
- dev_warn(dev, "thermtrip: %s: missing critical temperature\n",
- sg->name);
- goto set_throttle;
- }
+ /* Get thermtrips. If missing, try to get critical trips. */
+ temperature = tsensor_group_thermtrip_get(ts, sg->id);
+ if (min_low_temp == temperature)
+ if (tz->ops->get_crit_temp(tz, &temperature))
+ temperature = max_high_temp;
ret = thermtrip_program(dev, sg, temperature);
if (ret) {
- dev_err(dev, "thermtrip: %s: error during enable\n",
- sg->name);
+ dev_err(dev, "thermtrip: %s: error during enable\n", sg->name);
return ret;
}
- dev_info(dev,
- "thermtrip: will shut down when %s reaches %d mC\n",
+ dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n",
sg->name, temperature);
-set_throttle:
ret = get_hot_temp(tz, &trip, &temperature);
if (ret) {
dev_warn(dev, "throttrip: %s: missing hot temperature\n",
@@ -897,6 +920,50 @@ static const struct thermal_cooling_device_ops throt_cooling_ops = {
.set_cur_state = throt_set_cdev_state,
};
+static int soctherm_thermtrips_parse(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct tegra_soctherm *ts = dev_get_drvdata(dev);
+ struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
+ const int max_num_prop = ts->soc->num_ttgs * 2;
+ u32 *tlb;
+ int i, j, n, ret;
+
+ if (!tt)
+ return -ENOMEM;
+
+ n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips");
+ if (n <= 0) {
+ dev_info(dev,
+ "missing thermtrips, will use critical trips as shut down temp\n");
+ return n;
+ }
+
+ n = min(max_num_prop, n);
+
+ tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL);
+ if (!tlb)
+ return -ENOMEM;
+ ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips",
+ tlb, n);
+ if (ret) {
+ dev_err(dev, "invalid num ele: thermtrips:%d\n", ret);
+ return ret;
+ }
+
+ i = 0;
+ for (j = 0; j < n; j = j + 2) {
+ if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM)
+ continue;
+
+ tt[i].id = tlb[j];
+ tt[i].temp = tlb[j+1];
+ i++;
+ }
+
+ return 0;
+}
+
/**
* soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
* and register them as cooling devices.
@@ -1338,6 +1405,8 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
if (err)
return err;
+ soctherm_thermtrips_parse(pdev);
+
soctherm_init_hw_throt_cdev(pdev);
soctherm_init(pdev);
diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h
index e96ca73fd780..c05c7e37e968 100644
--- a/drivers/thermal/tegra/soctherm.h
+++ b/drivers/thermal/tegra/soctherm.h
@@ -92,6 +92,11 @@ struct tegra_tsensor {
const struct tegra_tsensor_group *group;
};
+struct tsensor_group_thermtrips {
+ u8 id;
+ u32 temp;
+};
+
struct tegra_soctherm_fuse {
u32 fuse_base_cp_mask, fuse_base_cp_shift;
u32 fuse_base_ft_mask, fuse_base_ft_shift;
@@ -113,6 +118,7 @@ struct tegra_soctherm_soc {
const int thresh_grain;
const unsigned int bptt;
const bool use_ccroc;
+ struct tsensor_group_thermtrips *thermtrips;
};
int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
diff --git a/drivers/thermal/tegra/tegra210-soctherm.c b/drivers/thermal/tegra/tegra210-soctherm.c
index ad53169a8e95..0a0c3cec7134 100644
--- a/drivers/thermal/tegra/tegra210-soctherm.c
+++ b/drivers/thermal/tegra/tegra210-soctherm.c
@@ -203,6 +203,13 @@ static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
.fuse_spare_realignment = 0,
};
+struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {
+ {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
+ {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
+ {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
+ {.id = TEGRA124_SOCTHERM_SENSOR_NUM},
+};
+
const struct tegra_soctherm_soc tegra210_soctherm = {
.tsensors = tegra210_tsensors,
.num_tsensors = ARRAY_SIZE(tegra210_tsensors),
@@ -212,4 +219,5 @@ const struct tegra_soctherm_soc tegra210_soctherm = {
.thresh_grain = TEGRA210_THRESH_GRAIN,
.bptt = TEGRA210_BPTT,
.use_ccroc = false,
+ .thermtrips = tegra210_tsensor_thermtrips,
};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 03/12] arm64: dts: tegra210: set thermtrip
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
2019-02-21 10:18 ` [PATCH v2 01/12] of: Add bindings of thermtrip " Wei Ni
2019-02-21 10:18 ` [PATCH v2 02/12] thermal: tegra: support hw and sw shutdown Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-04-26 3:21 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 04/12] of: Add bindings of gpu hw throttle for Tegra soctherm Wei Ni
` (9 subsequent siblings)
12 siblings, 1 reply; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Set "nvidia,thermtrips" property, it used to set
HW shutdown temperatures.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 6574396d2257..582d56820bbb 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1410,6 +1410,9 @@
reset-names = "soctherm";
#thermal-sensor-cells = <1>;
+ nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
+ TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
+
throttle-cfgs {
throttle_heavy: heavy {
nvidia,priority = <100>;
@@ -1429,8 +1432,8 @@
<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
trips {
- cpu-shutdown-trip {
- temperature = <102500>;
+ cpu-critical-trip {
+ temperature = <102000>;
hysteresis = <0>;
type = "critical";
};
@@ -1457,7 +1460,7 @@
<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
trips {
- mem-shutdown-trip {
+ mem-critical-trip {
temperature = <103000>;
hysteresis = <0>;
type = "critical";
@@ -1479,8 +1482,8 @@
<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
trips {
- gpu-shutdown-trip {
- temperature = <103000>;
+ gpu-critical-trip {
+ temperature = <102500>;
hysteresis = <0>;
type = "critical";
};
@@ -1507,7 +1510,7 @@
<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
trips {
- pllx-shutdown-trip {
+ pllx-critical-trip {
temperature = <103000>;
hysteresis = <0>;
type = "critical";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 03/12] arm64: dts: tegra210: set thermtrip
2019-02-21 10:18 ` [PATCH v2 03/12] arm64: dts: tegra210: set thermtrip Wei Ni
@ 2019-04-26 3:21 ` Wei Ni
0 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-04-26 3:21 UTC (permalink / raw)
To: thierry.reding
Cc: daniel.lezcano, edubezval, robh, linux-tegra, rui.zhang, srikars,
linux-kernel, linux-pm, devicetree
Hi Thierry,
Eduardo have picked this series to his branch except dts patches.
Please check
"git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git"
in the linus branch. They will be merged in the next major kernel release.
Could you please take these three dts changes?
Here is the list:
[PATCH v2 03/12] arm64: dts: tegra210: set thermtrip
[PATCH v2 06/12] arm64: dts: tegra210: set gpu hw throttle level
[PATCH v2 10/12] arm64: dts: tegra210: set EDP interrupt line
Thanks.
Wei.
On 21/2/2019 6:18 PM, Wei Ni wrote:
> Set "nvidia,thermtrips" property, it used to set
> HW shutdown temperatures.
>
> Signed-off-by: Wei Ni <wni@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> index 6574396d2257..582d56820bbb 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> @@ -1410,6 +1410,9 @@
> reset-names = "soctherm";
> #thermal-sensor-cells = <1>;
>
> + nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
> + TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
> +
> throttle-cfgs {
> throttle_heavy: heavy {
> nvidia,priority = <100>;
> @@ -1429,8 +1432,8 @@
> <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
>
> trips {
> - cpu-shutdown-trip {
> - temperature = <102500>;
> + cpu-critical-trip {
> + temperature = <102000>;
> hysteresis = <0>;
> type = "critical";
> };
> @@ -1457,7 +1460,7 @@
> <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
>
> trips {
> - mem-shutdown-trip {
> + mem-critical-trip {
> temperature = <103000>;
> hysteresis = <0>;
> type = "critical";
> @@ -1479,8 +1482,8 @@
> <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
>
> trips {
> - gpu-shutdown-trip {
> - temperature = <103000>;
> + gpu-critical-trip {
> + temperature = <102500>;
> hysteresis = <0>;
> type = "critical";
> };
> @@ -1507,7 +1510,7 @@
> <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
>
> trips {
> - pllx-shutdown-trip {
> + pllx-critical-trip {
> temperature = <103000>;
> hysteresis = <0>;
> type = "critical";
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 04/12] of: Add bindings of gpu hw throttle for Tegra soctherm
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (2 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 03/12] arm64: dts: tegra210: set thermtrip Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 05/12] thermal: tegra: add support for gpu hw-throttle Wei Ni
` (8 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Add "nvidia,gpu-throt-level" property to set gpu hw
throttle level.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
.../bindings/thermal/nvidia,tegra124-soctherm.txt | 17 +++++++++++++++--
include/dt-bindings/thermal/tegra124-soctherm.h | 8 ++++----
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
index ab66d6feab4b..cf6d0be56b7a 100644
--- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
+++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
@@ -52,6 +52,15 @@ Required properties :
Must set as following values:
TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
+ - nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
+ It is the level of pulse skippers, which used to throttle clock
+ frequencies. It indicates gpu clock throttling depth and can be
+ programmed to any of the following values which represent a throttling
+ percentage:
+ TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
+ TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
+ TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
+ TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%).
- #cooling-cells: Should be 1. This cooling device only support on/off state.
See ./thermal.txt for a description of this property.
@@ -96,22 +105,26 @@ Example :
throttle-cfgs {
/*
* When the "heavy" cooling device triggered,
- * the HW will skip cpu clock's pulse in 85% depth
+ * the HW will skip cpu clock's pulse in 85% depth,
+ * skip gpu clock's pulse in 85% level
*/
throttle_heavy: heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-percent = <85>;
+ nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
#cooling-cells = <1>;
};
/*
* When the "light" cooling device triggered,
- * the HW will skip cpu clock's pulse in 50% depth
+ * the HW will skip cpu clock's pulse in 50% depth,
+ * skip gpu clock's pulse in 50% level
*/
throttle_light: light {
nvidia,priority = <80>;
nvidia,cpu-throt-percent = <50>;
+ nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
#cooling-cells = <1>;
};
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
index c15e8b709a0d..444c7bdde146 100644
--- a/include/dt-bindings/thermal/tegra124-soctherm.h
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -12,9 +12,9 @@
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
#define TEGRA124_SOCTHERM_SENSOR_NUM 4
-#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 0
-#define TEGRA_SOCTHERM_THROT_LEVEL_MED 1
-#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 2
-#define TEGRA_SOCTHERM_THROT_LEVEL_NONE -1
+#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0
+#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1
+#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2
+#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 05/12] thermal: tegra: add support for gpu hw-throttle
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (3 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 04/12] of: Add bindings of gpu hw throttle for Tegra soctherm Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 06/12] arm64: dts: tegra210: set gpu hw throttle level Wei Ni
` (7 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Add support to trigger pulse skippers on the GPU
when a HOT trip point is triggered. The pulse skippers
can be signalled to throttle at low, medium and high
depths\levels.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/soctherm.c | 118 ++++++++++++++++++++++++++++-----------
1 file changed, 85 insertions(+), 33 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index 4bb6c097c028..edbb90da1ac3 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -1,5 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Mikko Perttunen <mperttunen@nvidia.com>
@@ -160,6 +161,15 @@
/* get dividend from the depth */
#define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
+/* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-sochterm.h
+ * level vector
+ * NONE 3'b000
+ * LOW 3'b001
+ * MED 3'b011
+ * HIGH 3'b111
+ */
+#define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
+
/* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */
#define THROT_OFFSET 0x30
#define THROT_PSKIP_CTRL(throt, dev) (THROT_PSKIP_CTRL_LITE_CPU + \
@@ -219,6 +229,7 @@ struct soctherm_throt_cfg {
u8 priority;
u8 cpu_throt_level;
u32 cpu_throt_depth;
+ u32 gpu_throt_level;
struct thermal_cooling_device *cdev;
bool init;
};
@@ -964,6 +975,50 @@ static int soctherm_thermtrips_parse(struct platform_device *pdev)
return 0;
}
+static int soctherm_throt_cfg_parse(struct device *dev,
+ struct device_node *np,
+ struct soctherm_throt_cfg *stc)
+{
+ struct tegra_soctherm *ts = dev_get_drvdata(dev);
+ int ret;
+ u32 val;
+
+ ret = of_property_read_u32(np, "nvidia,priority", &val);
+ if (ret) {
+ dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name);
+ return -EINVAL;
+ }
+ stc->priority = val;
+
+ ret = of_property_read_u32(np, ts->soc->use_ccroc ?
+ "nvidia,cpu-throt-level" :
+ "nvidia,cpu-throt-percent", &val);
+ if (!ret) {
+ if (ts->soc->use_ccroc &&
+ val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
+ stc->cpu_throt_level = val;
+ else if (!ts->soc->use_ccroc && val <= 100)
+ stc->cpu_throt_depth = val;
+ else
+ goto err;
+ } else {
+ goto err;
+ }
+
+ ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);
+ if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
+ stc->gpu_throt_level = val;
+ else
+ goto err;
+
+ return 0;
+
+err:
+ dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n",
+ stc->name);
+ return -EINVAL;
+}
+
/**
* soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
* and register them as cooling devices.
@@ -974,8 +1029,7 @@ static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
struct tegra_soctherm *ts = dev_get_drvdata(dev);
struct device_node *np_stc, *np_stcc;
const char *name;
- u32 val;
- int i, r;
+ int i;
for (i = 0; i < THROTTLE_SIZE; i++) {
ts->throt_cfgs[i].name = throt_names[i];
@@ -993,6 +1047,7 @@ static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
for_each_child_of_node(np_stc, np_stcc) {
struct soctherm_throt_cfg *stc;
struct thermal_cooling_device *tcd;
+ int err;
name = np_stcc->name;
stc = find_throttle_cfg_by_name(ts, name);
@@ -1002,37 +1057,10 @@ static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
continue;
}
- r = of_property_read_u32(np_stcc, "nvidia,priority", &val);
- if (r) {
- dev_info(dev,
- "throttle-cfg: %s: missing priority\n", name);
+
+ err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
+ if (err)
continue;
- }
- stc->priority = val;
-
- if (ts->soc->use_ccroc) {
- r = of_property_read_u32(np_stcc,
- "nvidia,cpu-throt-level",
- &val);
- if (r) {
- dev_info(dev,
- "throttle-cfg: %s: missing cpu-throt-level\n",
- name);
- continue;
- }
- stc->cpu_throt_level = val;
- } else {
- r = of_property_read_u32(np_stcc,
- "nvidia,cpu-throt-percent",
- &val);
- if (r) {
- dev_info(dev,
- "throttle-cfg: %s: missing cpu-throt-percent\n",
- name);
- continue;
- }
- stc->cpu_throt_depth = val;
- }
tcd = thermal_of_cooling_device_register(np_stcc,
(char *)name, ts,
@@ -1176,6 +1204,28 @@ static void throttlectl_cpu_mn(struct tegra_soctherm *ts,
}
/**
+ * throttlectl_gpu_level_select() - selects throttling level for GPU
+ * @throt: the LIGHT/HEAVY of throttle event id
+ *
+ * This function programs soctherm's interface to GK20a NV_THERM to select
+ * pre-configured "Low", "Medium" or "Heavy" throttle levels.
+ *
+ * Return: boolean true if HW was programmed
+ */
+static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
+ enum soctherm_throttle_id throt)
+{
+ u32 r, level, throt_vect;
+
+ level = ts->throt_cfgs[throt].gpu_throt_level;
+ throt_vect = THROT_LEVEL_TO_DEPTH(level);
+ r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
+ writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
+}
+
+/**
* soctherm_throttle_program() - programs pulse skippers' configuration
* @throt: the LIGHT/HEAVY of the throttle event id.
*
@@ -1197,6 +1247,8 @@ static void soctherm_throttle_program(struct tegra_soctherm *ts,
else
throttlectl_cpu_mn(ts, throt);
+ throttlectl_gpu_level_select(ts, throt);
+
r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 06/12] arm64: dts: tegra210: set gpu hw throttle level
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (4 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 05/12] thermal: tegra: add support for gpu hw-throttle Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 07/12] thermal: tegra: add support for thermal IRQ Wei Ni
` (6 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Set gpu hw throttle level to TEGRA_SOCTHERM_THROT_LEVEL_HIGH
Signed-off-by: Wei Ni <wni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 582d56820bbb..551600513c1a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1417,6 +1417,8 @@
throttle_heavy: heavy {
nvidia,priority = <100>;
nvidia,cpu-throt-percent = <85>;
+ nvidia,gpu-throt-level =
+ <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
#cooling-cells = <2>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 07/12] thermal: tegra: add support for thermal IRQ
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (5 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 06/12] arm64: dts: tegra210: set gpu hw throttle level Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 08/12] thermal: tegra: add set_trips functionality Wei Ni
` (5 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Support to generate an interrupt when the temperature
crosses a programmed threshold and notify the thermal framework.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/soctherm.c | 136 +++++++++++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index edbb90da1ac3..16275de2d67b 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -86,6 +86,20 @@
#define THERMCTL_LVL0_UP_STATS 0x10
#define THERMCTL_LVL0_DN_STATS 0x14
+#define THERMCTL_INTR_STATUS 0x84
+#define THERMCTL_INTR_ENABLE 0x88
+#define THERMCTL_INTR_DISABLE 0x8c
+
+#define TH_INTR_MD0_MASK BIT(25)
+#define TH_INTR_MU0_MASK BIT(24)
+#define TH_INTR_GD0_MASK BIT(17)
+#define TH_INTR_GU0_MASK BIT(16)
+#define TH_INTR_CD0_MASK BIT(9)
+#define TH_INTR_CU0_MASK BIT(8)
+#define TH_INTR_PD0_MASK BIT(1)
+#define TH_INTR_PU0_MASK BIT(0)
+#define TH_INTR_IGNORE_MASK 0xFCFCFCFC
+
#define THERMCTL_STATS_CTL 0x94
#define STATS_CTL_CLR_DN 0x8
#define STATS_CTL_EN_DN 0x4
@@ -242,6 +256,8 @@ struct tegra_soctherm {
void __iomem *clk_regs;
void __iomem *ccroc_regs;
+ int thermal_irq;
+
u32 *calib;
struct thermal_zone_device **thermctl_tzs;
struct tegra_soctherm_soc *soc;
@@ -640,6 +656,98 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
return 0;
}
+static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id)
+{
+ struct tegra_soctherm *ts = dev_id;
+ u32 r;
+
+ r = readl(ts->regs + THERMCTL_INTR_STATUS);
+ writel(r, ts->regs + THERMCTL_INTR_DISABLE);
+
+ return IRQ_WAKE_THREAD;
+}
+
+/**
+ * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
+ * @irq: The interrupt number being requested; not used
+ * @dev_id: Opaque pointer to tegra_soctherm;
+ *
+ * Clears the interrupt status register if there are expected
+ * interrupt bits set.
+ * The interrupt(s) are then handled by updating the corresponding
+ * thermal zones.
+ *
+ * An error is logged if any unexpected interrupt bits are set.
+ *
+ * Disabled interrupts are re-enabled.
+ *
+ * Return: %IRQ_HANDLED. Interrupt was handled and no further processing
+ * is needed.
+ */
+static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id)
+{
+ struct tegra_soctherm *ts = dev_id;
+ struct thermal_zone_device *tz;
+ u32 st, ex = 0, cp = 0, gp = 0, pl = 0, me = 0;
+
+ st = readl(ts->regs + THERMCTL_INTR_STATUS);
+
+ /* deliberately clear expected interrupts handled in SW */
+ cp |= st & TH_INTR_CD0_MASK;
+ cp |= st & TH_INTR_CU0_MASK;
+
+ gp |= st & TH_INTR_GD0_MASK;
+ gp |= st & TH_INTR_GU0_MASK;
+
+ pl |= st & TH_INTR_PD0_MASK;
+ pl |= st & TH_INTR_PU0_MASK;
+
+ me |= st & TH_INTR_MD0_MASK;
+ me |= st & TH_INTR_MU0_MASK;
+
+ ex |= cp | gp | pl | me;
+ if (ex) {
+ writel(ex, ts->regs + THERMCTL_INTR_STATUS);
+ st &= ~ex;
+
+ if (cp) {
+ tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU];
+ thermal_zone_device_update(tz,
+ THERMAL_EVENT_UNSPECIFIED);
+ }
+
+ if (gp) {
+ tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU];
+ thermal_zone_device_update(tz,
+ THERMAL_EVENT_UNSPECIFIED);
+ }
+
+ if (pl) {
+ tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX];
+ thermal_zone_device_update(tz,
+ THERMAL_EVENT_UNSPECIFIED);
+ }
+
+ if (me) {
+ tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM];
+ thermal_zone_device_update(tz,
+ THERMAL_EVENT_UNSPECIFIED);
+ }
+ }
+
+ /* deliberately ignore expected interrupts NOT handled in SW */
+ ex |= TH_INTR_IGNORE_MASK;
+ st &= ~ex;
+
+ if (st) {
+ /* Whine about any other unexpected INTR bits still set */
+ pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st);
+ writel(st, ts->regs + THERMCTL_INTR_STATUS);
+ }
+
+ return IRQ_HANDLED;
+}
+
#ifdef CONFIG_DEBUG_FS
static int regs_show(struct seq_file *s, void *data)
{
@@ -1302,6 +1410,32 @@ static void tegra_soctherm_throttle(struct device *dev)
writel(v, ts->regs + THERMCTL_STATS_CTL);
}
+static int soctherm_interrupts_init(struct platform_device *pdev,
+ struct tegra_soctherm *tegra)
+{
+ int ret;
+
+ tegra->thermal_irq = platform_get_irq(pdev, 0);
+ if (tegra->thermal_irq < 0) {
+ dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");
+ return 0;
+ }
+
+ ret = devm_request_threaded_irq(&pdev->dev,
+ tegra->thermal_irq,
+ soctherm_thermal_isr,
+ soctherm_thermal_isr_thread,
+ IRQF_ONESHOT,
+ dev_name(&pdev->dev),
+ tegra);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
static void soctherm_init(struct platform_device *pdev)
{
struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
@@ -1495,6 +1629,8 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
goto disable_clocks;
}
+ err = soctherm_interrupts_init(pdev, tegra);
+
soctherm_debug_init(pdev);
return 0;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 08/12] thermal: tegra: add set_trips functionality
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (6 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 07/12] thermal: tegra: add support for thermal IRQ Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 09/12] thermal: tegra: add support for EDP IRQ Wei Ni
` (4 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Implement set_trips ops to set passive trip points.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/soctherm.c | 64 ++++++++++++++++++++++++++++++-
drivers/thermal/tegra/soctherm.h | 10 +++++
drivers/thermal/tegra/tegra124-soctherm.c | 7 +++-
drivers/thermal/tegra/tegra132-soctherm.c | 7 +++-
drivers/thermal/tegra/tegra210-soctherm.c | 7 +++-
5 files changed, 90 insertions(+), 5 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index 16275de2d67b..69a0d553ec9e 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -87,8 +87,6 @@
#define THERMCTL_LVL0_DN_STATS 0x14
#define THERMCTL_INTR_STATUS 0x84
-#define THERMCTL_INTR_ENABLE 0x88
-#define THERMCTL_INTR_DISABLE 0x8c
#define TH_INTR_MD0_MASK BIT(25)
#define TH_INTR_MU0_MASK BIT(24)
@@ -265,6 +263,8 @@ struct tegra_soctherm {
struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE];
struct dentry *debugfs_dir;
+
+ struct mutex thermctl_lock;
};
/**
@@ -542,9 +542,59 @@ static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp)
return 0;
}
+static void thermal_irq_enable(struct tegra_thermctl_zone *zn)
+{
+ u32 r;
+
+ /* multiple zones could be handling and setting trips at once */
+ mutex_lock(&zn->ts->thermctl_lock);
+ r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE);
+ r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
+ writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);
+ mutex_unlock(&zn->ts->thermctl_lock);
+}
+
+static void thermal_irq_disable(struct tegra_thermctl_zone *zn)
+{
+ u32 r;
+
+ /* multiple zones could be handling and setting trips at once */
+ mutex_lock(&zn->ts->thermctl_lock);
+ r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE);
+ r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
+ writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);
+ mutex_unlock(&zn->ts->thermctl_lock);
+}
+
+static int tegra_thermctl_set_trips(void *data, int lo, int hi)
+{
+ struct tegra_thermctl_zone *zone = data;
+ u32 r;
+
+ thermal_irq_disable(zone);
+
+ r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset);
+ r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
+ writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
+
+ lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain;
+ hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain;
+ dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo);
+
+ r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
+ r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
+ r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
+ writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
+
+ thermal_irq_enable(zone);
+
+ return 0;
+}
+
static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
.get_temp = tegra_thermctl_get_temp,
.set_trip_temp = tegra_thermctl_set_trip_temp,
+ .set_trips = tegra_thermctl_set_trips,
};
static int get_hot_temp(struct thermal_zone_device *tz, int *trip, int *temp)
@@ -661,6 +711,15 @@ static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id)
struct tegra_soctherm *ts = dev_id;
u32 r;
+ /* Case for no lock:
+ * Although interrupts are enabled in set_trips, there is still no need
+ * to lock here because the interrupts are disabled before programming
+ * new trip points. Hence there cant be a interrupt on the same sensor.
+ * An interrupt can however occur on a sensor while trips are being
+ * programmed on a different one. This beign a LEVEL interrupt won't
+ * cause a new interrupt but this is taken care of by the re-reading of
+ * the STATUS register in the thread function.
+ */
r = readl(ts->regs + THERMCTL_INTR_STATUS);
writel(r, ts->regs + THERMCTL_INTR_DISABLE);
@@ -1513,6 +1572,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
if (!tegra)
return -ENOMEM;
+ mutex_init(&tegra->thermctl_lock);
dev_set_drvdata(&pdev->dev, tegra);
tegra->soc = soc;
diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h
index c05c7e37e968..70501e73d586 100644
--- a/drivers/thermal/tegra/soctherm.h
+++ b/drivers/thermal/tegra/soctherm.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
*
@@ -29,6 +30,14 @@
#define THERMCTL_THERMTRIP_CTL 0x80
/* BITs are defined in device file */
+#define THERMCTL_INTR_ENABLE 0x88
+#define THERMCTL_INTR_DISABLE 0x8c
+#define TH_INTR_UP_DN_EN 0x3
+#define THERM_IRQ_MEM_MASK (TH_INTR_UP_DN_EN << 24)
+#define THERM_IRQ_GPU_MASK (TH_INTR_UP_DN_EN << 16)
+#define THERM_IRQ_CPU_MASK (TH_INTR_UP_DN_EN << 8)
+#define THERM_IRQ_TSENSE_MASK (TH_INTR_UP_DN_EN << 0)
+
#define SENSOR_PDIV 0x1c0
#define SENSOR_PDIV_CPU_MASK (0xf << 12)
#define SENSOR_PDIV_GPU_MASK (0xf << 8)
@@ -70,6 +79,7 @@ struct tegra_tsensor_group {
u32 thermtrip_enable_mask;
u32 thermtrip_any_en_mask;
u32 thermtrip_threshold_mask;
+ u32 thermctl_isr_mask;
u16 thermctl_lvl0_offset;
u32 thermctl_lvl0_up_thresh_mask;
u32 thermctl_lvl0_dn_thresh_mask;
diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/tegra/tegra124-soctherm.c
index 36768630f78c..20ad27f4d1a1 100644
--- a/drivers/thermal/tegra/tegra124-soctherm.c
+++ b/drivers/thermal/tegra/tegra124-soctherm.c
@@ -1,5 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -55,6 +56,7 @@ static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
.thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK,
.thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
.thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -73,6 +75,7 @@ static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
.thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK,
.thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
.thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -89,6 +92,7 @@ static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
.thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK,
.thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
.thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -107,6 +111,7 @@ static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
.thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK,
.thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
.thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
diff --git a/drivers/thermal/tegra/tegra132-soctherm.c b/drivers/thermal/tegra/tegra132-soctherm.c
index 97fa30501eb1..b76308fdad9e 100644
--- a/drivers/thermal/tegra/tegra132-soctherm.c
+++ b/drivers/thermal/tegra/tegra132-soctherm.c
@@ -1,5 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -55,6 +56,7 @@ static const struct tegra_tsensor_group tegra132_tsensor_group_cpu = {
.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA132_THERMTRIP_CPU_EN_MASK,
.thermtrip_threshold_mask = TEGRA132_THERMTRIP_CPU_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -73,6 +75,7 @@ static const struct tegra_tsensor_group tegra132_tsensor_group_gpu = {
.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA132_THERMTRIP_GPU_EN_MASK,
.thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -89,6 +92,7 @@ static const struct tegra_tsensor_group tegra132_tsensor_group_pll = {
.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA132_THERMTRIP_TSENSE_EN_MASK,
.thermtrip_threshold_mask = TEGRA132_THERMTRIP_TSENSE_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -107,6 +111,7 @@ static const struct tegra_tsensor_group tegra132_tsensor_group_mem = {
.thermtrip_any_en_mask = TEGRA132_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA132_THERMTRIP_MEM_EN_MASK,
.thermtrip_threshold_mask = TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
.thermctl_lvl0_up_thresh_mask = TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK,
diff --git a/drivers/thermal/tegra/tegra210-soctherm.c b/drivers/thermal/tegra/tegra210-soctherm.c
index 0a0c3cec7134..d31b50050faa 100644
--- a/drivers/thermal/tegra/tegra210-soctherm.c
+++ b/drivers/thermal/tegra/tegra210-soctherm.c
@@ -1,5 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -56,6 +57,7 @@ static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = {
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -74,6 +76,7 @@ static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = {
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -90,6 +93,7 @@ static const struct tegra_tsensor_group tegra210_tsensor_group_pll = {
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
@@ -108,6 +112,7 @@ static const struct tegra_tsensor_group tegra210_tsensor_group_mem = {
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 09/12] thermal: tegra: add support for EDP IRQ
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (7 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 08/12] thermal: tegra: add set_trips functionality Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 10/12] arm64: dts: tegra210: set EDP interrupt line Wei Ni
` (3 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Add support to generate OC (over-current) interrupts to
indicate the OC event and print out alarm messages.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/soctherm.c | 420 +++++++++++++++++++++++++++++++++++++++
1 file changed, 420 insertions(+)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index 69a0d553ec9e..b8c66368e54e 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -23,6 +23,8 @@
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@@ -104,6 +106,16 @@
#define STATS_CTL_CLR_UP 0x2
#define STATS_CTL_EN_UP 0x1
+#define OC_INTR_STATUS 0x39c
+#define OC_INTR_ENABLE 0x3a0
+#define OC_INTR_DISABLE 0x3a4
+
+#define OC_INTR_OC1_MASK BIT(0)
+#define OC_INTR_OC2_MASK BIT(1)
+#define OC_INTR_OC3_MASK BIT(2)
+#define OC_INTR_OC4_MASK BIT(3)
+#define OC_INTR_OC5_MASK BIT(4)
+
#define THROT_GLOBAL_CFG 0x400
#define THROT_GLOBAL_ENB_MASK BIT(0)
@@ -212,9 +224,23 @@ static const int max_high_temp = 127000;
enum soctherm_throttle_id {
THROTTLE_LIGHT = 0,
THROTTLE_HEAVY,
+ THROTTLE_OC1,
+ THROTTLE_OC2,
+ THROTTLE_OC3,
+ THROTTLE_OC4,
+ THROTTLE_OC5, /* OC5 is reserved */
THROTTLE_SIZE,
};
+enum soctherm_oc_irq_id {
+ TEGRA_SOC_OC_IRQ_1,
+ TEGRA_SOC_OC_IRQ_2,
+ TEGRA_SOC_OC_IRQ_3,
+ TEGRA_SOC_OC_IRQ_4,
+ TEGRA_SOC_OC_IRQ_5,
+ TEGRA_SOC_OC_IRQ_MAX,
+};
+
enum soctherm_throttle_dev_id {
THROTTLE_DEV_CPU = 0,
THROTTLE_DEV_GPU,
@@ -224,6 +250,11 @@ enum soctherm_throttle_dev_id {
static const char *const throt_names[] = {
[THROTTLE_LIGHT] = "light",
[THROTTLE_HEAVY] = "heavy",
+ [THROTTLE_OC1] = "oc1",
+ [THROTTLE_OC2] = "oc2",
+ [THROTTLE_OC3] = "oc3",
+ [THROTTLE_OC4] = "oc4",
+ [THROTTLE_OC5] = "oc5",
};
struct tegra_soctherm;
@@ -255,6 +286,7 @@ struct tegra_soctherm {
void __iomem *ccroc_regs;
int thermal_irq;
+ int edp_irq;
u32 *calib;
struct thermal_zone_device **thermctl_tzs;
@@ -267,6 +299,15 @@ struct tegra_soctherm {
struct mutex thermctl_lock;
};
+struct soctherm_oc_irq_chip_data {
+ struct mutex irq_lock; /* serialize OC IRQs */
+ struct irq_chip irq_chip;
+ struct irq_domain *domain;
+ int irq_enable;
+};
+
+static struct soctherm_oc_irq_chip_data soc_irq_cdata;
+
/**
* ccroc_writel() - writes a value to a CCROC register
* @ts: pointer to a struct tegra_soctherm
@@ -807,6 +848,360 @@ static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id)
return IRQ_HANDLED;
}
+/**
+ * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
+ * @alarm: The soctherm throttle id
+ * @enable: Flag indicating enable the soctherm over-current
+ * interrupt or disable it
+ *
+ * Enables a specific over-current pins @alarm to raise an interrupt if the flag
+ * is set and the alarm corresponds to OC1, OC2, OC3, or OC4.
+ */
+static void soctherm_oc_intr_enable(struct tegra_soctherm *ts,
+ enum soctherm_throttle_id alarm,
+ bool enable)
+{
+ u32 r;
+
+ if (!enable)
+ return;
+
+ r = readl(ts->regs + OC_INTR_ENABLE);
+ switch (alarm) {
+ case THROTTLE_OC1:
+ r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
+ break;
+ case THROTTLE_OC2:
+ r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
+ break;
+ case THROTTLE_OC3:
+ r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
+ break;
+ case THROTTLE_OC4:
+ r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);
+ break;
+ default:
+ r = 0;
+ break;
+ }
+ writel(r, ts->regs + OC_INTR_ENABLE);
+}
+
+/**
+ * soctherm_handle_alarm() - Handles soctherm alarms
+ * @alarm: The soctherm throttle id
+ *
+ * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
+ * a warning or informative message.
+ *
+ * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
+ */
+static int soctherm_handle_alarm(enum soctherm_throttle_id alarm)
+{
+ int rv = -EINVAL;
+
+ switch (alarm) {
+ case THROTTLE_OC1:
+ pr_debug("soctherm: Successfully handled OC1 alarm\n");
+ rv = 0;
+ break;
+
+ case THROTTLE_OC2:
+ pr_debug("soctherm: Successfully handled OC2 alarm\n");
+ rv = 0;
+ break;
+
+ case THROTTLE_OC3:
+ pr_debug("soctherm: Successfully handled OC3 alarm\n");
+ rv = 0;
+ break;
+
+ case THROTTLE_OC4:
+ pr_debug("soctherm: Successfully handled OC4 alarm\n");
+ rv = 0;
+ break;
+
+ default:
+ break;
+ }
+
+ if (rv)
+ pr_err("soctherm: ERROR in handling %s alarm\n",
+ throt_names[alarm]);
+
+ return rv;
+}
+
+/**
+ * soctherm_edp_isr_thread() - log an over-current interrupt request
+ * @irq: OC irq number. Currently not being used. See description
+ * @arg: a void pointer for callback, currently not being used
+ *
+ * Over-current events are handled in hardware. This function is called to log
+ * and handle any OC events that happened. Additionally, it checks every
+ * over-current interrupt registers for registers are set but
+ * was not expected (i.e. any discrepancy in interrupt status) by the function,
+ * the discrepancy will logged.
+ *
+ * Return: %IRQ_HANDLED
+ */
+static irqreturn_t soctherm_edp_isr_thread(int irq, void *arg)
+{
+ struct tegra_soctherm *ts = arg;
+ u32 st, ex, oc1, oc2, oc3, oc4;
+
+ st = readl(ts->regs + OC_INTR_STATUS);
+
+ /* deliberately clear expected interrupts handled in SW */
+ oc1 = st & OC_INTR_OC1_MASK;
+ oc2 = st & OC_INTR_OC2_MASK;
+ oc3 = st & OC_INTR_OC3_MASK;
+ oc4 = st & OC_INTR_OC4_MASK;
+ ex = oc1 | oc2 | oc3 | oc4;
+
+ pr_err("soctherm: OC ALARM 0x%08x\n", ex);
+ if (ex) {
+ writel(st, ts->regs + OC_INTR_STATUS);
+ st &= ~ex;
+
+ if (oc1 && !soctherm_handle_alarm(THROTTLE_OC1))
+ soctherm_oc_intr_enable(ts, THROTTLE_OC1, true);
+
+ if (oc2 && !soctherm_handle_alarm(THROTTLE_OC2))
+ soctherm_oc_intr_enable(ts, THROTTLE_OC2, true);
+
+ if (oc3 && !soctherm_handle_alarm(THROTTLE_OC3))
+ soctherm_oc_intr_enable(ts, THROTTLE_OC3, true);
+
+ if (oc4 && !soctherm_handle_alarm(THROTTLE_OC4))
+ soctherm_oc_intr_enable(ts, THROTTLE_OC4, true);
+
+ if (oc1 && soc_irq_cdata.irq_enable & BIT(0))
+ handle_nested_irq(
+ irq_find_mapping(soc_irq_cdata.domain, 0));
+
+ if (oc2 && soc_irq_cdata.irq_enable & BIT(1))
+ handle_nested_irq(
+ irq_find_mapping(soc_irq_cdata.domain, 1));
+
+ if (oc3 && soc_irq_cdata.irq_enable & BIT(2))
+ handle_nested_irq(
+ irq_find_mapping(soc_irq_cdata.domain, 2));
+
+ if (oc4 && soc_irq_cdata.irq_enable & BIT(3))
+ handle_nested_irq(
+ irq_find_mapping(soc_irq_cdata.domain, 3));
+ }
+
+ if (st) {
+ pr_err("soctherm: Ignored unexpected OC ALARM 0x%08x\n", st);
+ writel(st, ts->regs + OC_INTR_STATUS);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * soctherm_edp_isr() - Disables any active interrupts
+ * @irq: The interrupt request number
+ * @arg: Opaque pointer to an argument
+ *
+ * Writes to the OC_INTR_DISABLE register the over current interrupt status,
+ * masking any asserted interrupts. Doing this prevents the same interrupts
+ * from triggering this isr repeatedly. The thread woken by this isr will
+ * handle asserted interrupts and subsequently unmask/re-enable them.
+ *
+ * The OC_INTR_DISABLE register indicates which OC interrupts
+ * have been disabled.
+ *
+ * Return: %IRQ_WAKE_THREAD, handler requests to wake the handler thread
+ */
+static irqreturn_t soctherm_edp_isr(int irq, void *arg)
+{
+ struct tegra_soctherm *ts = arg;
+ u32 r;
+
+ if (!ts)
+ return IRQ_NONE;
+
+ r = readl(ts->regs + OC_INTR_STATUS);
+ writel(r, ts->regs + OC_INTR_DISABLE);
+
+ return IRQ_WAKE_THREAD;
+}
+
+/**
+ * soctherm_oc_irq_lock() - locks the over-current interrupt request
+ * @data: Interrupt request data
+ *
+ * Looks up the chip data from @data and locks the mutex associated with
+ * a particular over-current interrupt request.
+ */
+static void soctherm_oc_irq_lock(struct irq_data *data)
+{
+ struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+
+ mutex_lock(&d->irq_lock);
+}
+
+/**
+ * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
+ * @data: Interrupt request data
+ *
+ * Looks up the interrupt request data @data and unlocks the mutex associated
+ * with a particular over-current interrupt request.
+ */
+static void soctherm_oc_irq_sync_unlock(struct irq_data *data)
+{
+ struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+
+ mutex_unlock(&d->irq_lock);
+}
+
+/**
+ * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
+ * @data: irq_data structure of the chip
+ *
+ * Sets the irq_enable bit of SOC_THERM allowing SOC_THERM
+ * to respond to over-current interrupts.
+ *
+ */
+static void soctherm_oc_irq_enable(struct irq_data *data)
+{
+ struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+
+ d->irq_enable |= BIT(data->hwirq);
+}
+
+/**
+ * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
+ * @irq_data: The interrupt request information
+ *
+ * Clears the interrupt request enable bit of the overcurrent
+ * interrupt request chip data.
+ *
+ * Return: Nothing is returned (void)
+ */
+static void soctherm_oc_irq_disable(struct irq_data *data)
+{
+ struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
+
+ d->irq_enable &= ~BIT(data->hwirq);
+}
+
+static int soctherm_oc_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ return 0;
+}
+
+/**
+ * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
+ * @h: Interrupt request domain
+ * @virq: Virtual interrupt request number
+ * @hw: Hardware interrupt request number
+ *
+ * Mapping callback function for SOC_THERM's irq_domain. When a SOC_THERM
+ * interrupt request is called, the irq_domain takes the request's virtual
+ * request number (much like a virtual memory address) and maps it to a
+ * physical hardware request number.
+ *
+ * When a mapping doesn't already exist for a virtual request number, the
+ * irq_domain calls this function to associate the virtual request number with
+ * a hardware request number.
+ *
+ * Return: 0
+ */
+static int soctherm_oc_irq_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct soctherm_oc_irq_chip_data *data = h->host_data;
+
+ irq_set_chip_data(virq, data);
+ irq_set_chip(virq, &data->irq_chip);
+ irq_set_nested_thread(virq, 1);
+ return 0;
+}
+
+/**
+ * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
+ * @d: Interrupt request domain
+ * @intspec: Array of u32s from DTs "interrupt" property
+ * @intsize: Number of values inside the intspec array
+ * @out_hwirq: HW IRQ value associated with this interrupt
+ * @out_type: The IRQ SENSE type for this interrupt.
+ *
+ * This Device Tree IRQ specifier translation function will translate a
+ * specific "interrupt" as defined by 2 DT values where the cell values map
+ * the hwirq number + 1 and linux irq flags. Since the output is the hwirq
+ * number, this function will subtract 1 from the value listed in DT.
+ *
+ * Return: 0
+ */
+static int soctherm_irq_domain_xlate_twocell(struct irq_domain *d,
+ struct device_node *ctrlr, const u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq, unsigned int *out_type)
+{
+ if (WARN_ON(intsize < 2))
+ return -EINVAL;
+
+ /*
+ * The HW value is 1 index less than the DT IRQ values.
+ * i.e. OC4 goes to HW index 3.
+ */
+ *out_hwirq = intspec[0] - 1;
+ *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
+ return 0;
+}
+
+static const struct irq_domain_ops soctherm_oc_domain_ops = {
+ .map = soctherm_oc_irq_map,
+ .xlate = soctherm_irq_domain_xlate_twocell,
+};
+
+/**
+ * soctherm_oc_int_init() - Initial enabling of the over
+ * current interrupts
+ * @np: The devicetree node for soctherm
+ * @num_irqs: The number of new interrupt requests
+ *
+ * Sets the over current interrupt request chip data
+ *
+ * Return: 0 on success or if overcurrent interrupts are not enabled,
+ * -ENOMEM (out of memory), or irq_base if the function failed to
+ * allocate the irqs
+ */
+static int soctherm_oc_int_init(struct device_node *np, int num_irqs)
+{
+ if (!num_irqs) {
+ pr_info("%s(): OC interrupts are not enabled\n", __func__);
+ return 0;
+ }
+
+ mutex_init(&soc_irq_cdata.irq_lock);
+ soc_irq_cdata.irq_enable = 0;
+
+ soc_irq_cdata.irq_chip.name = "soc_therm_oc";
+ soc_irq_cdata.irq_chip.irq_bus_lock = soctherm_oc_irq_lock;
+ soc_irq_cdata.irq_chip.irq_bus_sync_unlock =
+ soctherm_oc_irq_sync_unlock;
+ soc_irq_cdata.irq_chip.irq_disable = soctherm_oc_irq_disable;
+ soc_irq_cdata.irq_chip.irq_enable = soctherm_oc_irq_enable;
+ soc_irq_cdata.irq_chip.irq_set_type = soctherm_oc_irq_set_type;
+ soc_irq_cdata.irq_chip.irq_set_wake = NULL;
+
+ soc_irq_cdata.domain = irq_domain_add_linear(np, num_irqs,
+ &soctherm_oc_domain_ops,
+ &soc_irq_cdata);
+
+ if (!soc_irq_cdata.domain) {
+ pr_err("%s: Failed to create IRQ domain\n", __func__);
+ return -ENOMEM;
+ }
+
+ pr_debug("%s(): OC interrupts enabled successful\n", __func__);
+ return 0;
+}
+
#ifdef CONFIG_DEBUG_FS
static int regs_show(struct seq_file *s, void *data)
{
@@ -1472,14 +1867,27 @@ static void tegra_soctherm_throttle(struct device *dev)
static int soctherm_interrupts_init(struct platform_device *pdev,
struct tegra_soctherm *tegra)
{
+ struct device_node *np = pdev->dev.of_node;
int ret;
+ ret = soctherm_oc_int_init(np, TEGRA_SOC_OC_IRQ_MAX);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "soctherm_oc_int_init failed\n");
+ return ret;
+ }
+
tegra->thermal_irq = platform_get_irq(pdev, 0);
if (tegra->thermal_irq < 0) {
dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");
return 0;
}
+ tegra->edp_irq = platform_get_irq(pdev, 1);
+ if (tegra->edp_irq < 0) {
+ dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n");
+ return 0;
+ }
+
ret = devm_request_threaded_irq(&pdev->dev,
tegra->thermal_irq,
soctherm_thermal_isr,
@@ -1492,6 +1900,18 @@ static int soctherm_interrupts_init(struct platform_device *pdev,
return ret;
}
+ ret = devm_request_threaded_irq(&pdev->dev,
+ tegra->edp_irq,
+ soctherm_edp_isr,
+ soctherm_edp_isr_thread,
+ IRQF_ONESHOT,
+ "soctherm_edp",
+ tegra);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n");
+ return ret;
+ }
+
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 10/12] arm64: dts: tegra210: set EDP interrupt line
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (8 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 09/12] thermal: tegra: add support for EDP IRQ Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 11/12] of: Add bindings of OC hw throttle for Tegra soctherm Wei Ni
` (2 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Set EDP interrupt line.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 551600513c1a..19966b9f5ce7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1402,7 +1402,8 @@
reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
reg-names = "soctherm-reg", "car-reg";
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
<&tegra_car TEGRA210_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 11/12] of: Add bindings of OC hw throttle for Tegra soctherm
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (9 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 10/12] arm64: dts: tegra210: set EDP interrupt line Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-02-21 10:18 ` [PATCH v2 12/12] thermal: tegra: enable OC hw throttle Wei Ni
2019-03-26 2:17 ` [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Add OC HW throttle configuration for soctherm in DT.
It is used to describe the OCx throttle events.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
.../bindings/thermal/nvidia,tegra124-soctherm.txt | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
index cf6d0be56b7a..f02f38527a6b 100644
--- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
+++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt
@@ -64,6 +64,20 @@ Required properties :
- #cooling-cells: Should be 1. This cooling device only support on/off state.
See ./thermal.txt for a description of this property.
+ Optional properties: The following properties are T210 specific and
+ valid only for OCx throttle events.
+ - nvidia,count-threshold: Specifies the number of OC events that are
+ required for triggering an interrupt. Interrupts are not triggered if
+ the property is missing. A value of 0 will interrupt on every OC alarm.
+ - nvidia,polarity-active-low: Configures the polarity of the OC alaram
+ signal. If present, this means assert low, otherwise assert high.
+ - nvidia,alarm-filter: Number of clocks to filter event. When the filter
+ expires (which means the OC event has not occurred for a long time),
+ the counter is cleared and filter is rearmed. Default value is 0.
+ - nvidia,throttle-period-us: Specifies the number of uSec for which
+ throttling is engaged after the OC event is deasserted. Default value
+ is 0.
+
Optional properties:
- nvidia,thermtrips : When present, this property specifies the temperature at
which the soctherm hardware will assert the thermal trigger signal to the
@@ -134,6 +148,17 @@ Example :
* arbiter will select the highest priority as the final throttle
* settings to skip cpu pulse.
*/
+
+ throttle_oc1: oc1 {
+ nvidia,priority = <50>;
+ nvidia,polarity-active-low;
+ nvidia,count-threshold = <100>;
+ nvidia,alarm-filter = <5100000>;
+ nvidia,throttle-period-us = <0>;
+ nvidia,cpu-throt-percent = <75>;
+ nvidia,gpu-throt-level =
+ <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
+ };
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v2 12/12] thermal: tegra: enable OC hw throttle
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (10 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 11/12] of: Add bindings of OC hw throttle for Tegra soctherm Wei Ni
@ 2019-02-21 10:18 ` Wei Ni
2019-04-23 15:46 ` Eduardo Valentin
2019-03-26 2:17 ` [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
12 siblings, 1 reply; 18+ messages in thread
From: Wei Ni @ 2019-02-21 10:18 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree, Wei Ni
Parse Over Current settings from DT and program them to
generate interrupts. Also enable hw throttling whenever
there are OC events. Log the OC events as debug messages.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/soctherm.c | 130 ++++++++++++++++++++++++++++++++++++---
1 file changed, 120 insertions(+), 10 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index b8c66368e54e..6e3f329d1ac4 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -106,9 +106,26 @@
#define STATS_CTL_CLR_UP 0x2
#define STATS_CTL_EN_UP 0x1
+#define OC1_CFG 0x310
+#define OC1_CFG_LONG_LATENCY_MASK BIT(6)
+#define OC1_CFG_HW_RESTORE_MASK BIT(5)
+#define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4)
+#define OC1_CFG_THROTTLE_MODE_MASK (0x3 << 2)
+#define OC1_CFG_ALARM_POLARITY_MASK BIT(1)
+#define OC1_CFG_EN_THROTTLE_MASK BIT(0)
+
+#define OC1_CNT_THRESHOLD 0x314
+#define OC1_THROTTLE_PERIOD 0x318
+#define OC1_ALARM_COUNT 0x31c
+#define OC1_FILTER 0x320
+#define OC1_STATS 0x3a8
+
#define OC_INTR_STATUS 0x39c
#define OC_INTR_ENABLE 0x3a0
#define OC_INTR_DISABLE 0x3a4
+#define OC_STATS_CTL 0x3c4
+#define OC_STATS_CTL_CLR_ALL 0x2
+#define OC_STATS_CTL_EN_ALL 0x1
#define OC_INTR_OC1_MASK BIT(0)
#define OC_INTR_OC2_MASK BIT(1)
@@ -207,6 +224,25 @@
#define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
(THROT_OFFSET * throt))
+#define ALARM_OFFSET 0x14
+#define ALARM_CFG(throt) (OC1_CFG + \
+ (ALARM_OFFSET * (throt - THROTTLE_OC1)))
+
+#define ALARM_CNT_THRESHOLD(throt) (OC1_CNT_THRESHOLD + \
+ (ALARM_OFFSET * (throt - THROTTLE_OC1)))
+
+#define ALARM_THROTTLE_PERIOD(throt) (OC1_THROTTLE_PERIOD + \
+ (ALARM_OFFSET * (throt - THROTTLE_OC1)))
+
+#define ALARM_ALARM_COUNT(throt) (OC1_ALARM_COUNT + \
+ (ALARM_OFFSET * (throt - THROTTLE_OC1)))
+
+#define ALARM_FILTER(throt) (OC1_FILTER + \
+ (ALARM_OFFSET * (throt - THROTTLE_OC1)))
+
+#define ALARM_STATS(throt) (OC1_STATS + \
+ (4 * (throt - THROTTLE_OC1)))
+
/* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
#define CCROC_THROT_OFFSET 0x0c
#define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
@@ -218,6 +254,9 @@
#define THERMCTL_LVL_REGS_SIZE 0x20
#define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
+#define OC_THROTTLE_MODE_DISABLED 0
+#define OC_THROTTLE_MODE_BRIEF 2
+
static const int min_low_temp = -127000;
static const int max_high_temp = 127000;
@@ -266,6 +305,15 @@ struct tegra_thermctl_zone {
const struct tegra_tsensor_group *sg;
};
+struct soctherm_oc_cfg {
+ u32 active_low;
+ u32 throt_period;
+ u32 alarm_cnt_thresh;
+ u32 alarm_filter;
+ u32 mode;
+ bool intr_en;
+};
+
struct soctherm_throt_cfg {
const char *name;
unsigned int id;
@@ -273,6 +321,7 @@ struct soctherm_throt_cfg {
u8 cpu_throt_level;
u32 cpu_throt_depth;
u32 gpu_throt_level;
+ struct soctherm_oc_cfg oc_cfg;
struct thermal_cooling_device *cdev;
bool init;
};
@@ -715,7 +764,7 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
return 0;
}
- for (i = 0; i < THROTTLE_SIZE; i++) {
+ for (i = 0; i < THROTTLE_OC1; i++) {
struct thermal_cooling_device *cdev;
if (!ts->throt_cfgs[i].init)
@@ -1537,6 +1586,32 @@ static int soctherm_thermtrips_parse(struct platform_device *pdev)
return 0;
}
+static void soctherm_oc_cfg_parse(struct device *dev,
+ struct device_node *np_oc,
+ struct soctherm_throt_cfg *stc)
+{
+ u32 val;
+
+ if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
+ stc->oc_cfg.active_low = 1;
+ else
+ stc->oc_cfg.active_low = 0;
+
+ if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
+ stc->oc_cfg.intr_en = 1;
+ stc->oc_cfg.alarm_cnt_thresh = val;
+ }
+
+ if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
+ stc->oc_cfg.throt_period = val;
+
+ if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
+ stc->oc_cfg.alarm_filter = val;
+
+ /* BRIEF throttling by default, do not support STICKY */
+ stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
+}
+
static int soctherm_throt_cfg_parse(struct device *dev,
struct device_node *np,
struct soctherm_throt_cfg *stc)
@@ -1619,24 +1694,34 @@ static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
continue;
}
+ if (stc->init) {
+ dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
+ of_node_put(np_stcc);
+ break;
+ }
err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
if (err)
continue;
- tcd = thermal_of_cooling_device_register(np_stcc,
+ if (stc->id >= THROTTLE_OC1) {
+ soctherm_oc_cfg_parse(dev, np_stcc, stc);
+ stc->init = true;
+ } else {
+
+ tcd = thermal_of_cooling_device_register(np_stcc,
(char *)name, ts,
&throt_cooling_ops);
- of_node_put(np_stcc);
- if (IS_ERR_OR_NULL(tcd)) {
- dev_err(dev,
- "throttle-cfg: %s: failed to register cooling device\n",
- name);
- continue;
+ if (IS_ERR_OR_NULL(tcd)) {
+ dev_err(dev,
+ "throttle-cfg: %s: failed to register cooling device\n",
+ name);
+ continue;
+ }
+ stc->cdev = tcd;
+ stc->init = true;
}
- stc->cdev = tcd;
- stc->init = true;
}
of_node_put(np_stc);
@@ -1787,6 +1872,28 @@ static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
}
+static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
+ enum soctherm_throttle_id throt)
+{
+ u32 r;
+ struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
+
+ if (oc->mode == OC_THROTTLE_MODE_DISABLED)
+ return -EINVAL;
+
+ r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
+ r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
+ r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
+ r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
+ writel(r, ts->regs + ALARM_CFG(throt));
+ writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
+ writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
+ writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
+ soctherm_oc_intr_enable(ts, throt, oc->intr_en);
+
+ return 0;
+}
+
/**
* soctherm_throttle_program() - programs pulse skippers' configuration
* @throt: the LIGHT/HEAVY of the throttle event id.
@@ -1803,6 +1910,9 @@ static void soctherm_throttle_program(struct tegra_soctherm *ts,
if (!stc.init)
return;
+ if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
+ return;
+
/* Setup PSKIP parameters */
if (ts->soc->use_ccroc)
throttlectl_cpu_level_select(ts, throt);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 12/12] thermal: tegra: enable OC hw throttle
2019-02-21 10:18 ` [PATCH v2 12/12] thermal: tegra: enable OC hw throttle Wei Ni
@ 2019-04-23 15:46 ` Eduardo Valentin
2019-04-24 8:36 ` Wei Ni
0 siblings, 1 reply; 18+ messages in thread
From: Eduardo Valentin @ 2019-04-23 15:46 UTC (permalink / raw)
To: Wei Ni
Cc: daniel.lezcano, robh, thierry.reding, linux-tegra, rui.zhang,
srikars, linux-kernel, linux-pm, devicetree
On Thu, Feb 21, 2019 at 06:18:47PM +0800, Wei Ni wrote:
> Parse Over Current settings from DT and program them to
> generate interrupts. Also enable hw throttling whenever
> there are OC events. Log the OC events as debug messages.
>
> Signed-off-by: Wei Ni <wni@nvidia.com>
I applied this series except for this specific patch which:
a. does not apply clean
b. does not compile.
Please rebase on top of my -linus branch and resend this. remember to
checkpatch and compile and boot test before sending.
> ---
> drivers/thermal/tegra/soctherm.c | 130 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 120 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
> index b8c66368e54e..6e3f329d1ac4 100644
> --- a/drivers/thermal/tegra/soctherm.c
> +++ b/drivers/thermal/tegra/soctherm.c
> @@ -106,9 +106,26 @@
> #define STATS_CTL_CLR_UP 0x2
> #define STATS_CTL_EN_UP 0x1
>
> +#define OC1_CFG 0x310
> +#define OC1_CFG_LONG_LATENCY_MASK BIT(6)
> +#define OC1_CFG_HW_RESTORE_MASK BIT(5)
> +#define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4)
> +#define OC1_CFG_THROTTLE_MODE_MASK (0x3 << 2)
> +#define OC1_CFG_ALARM_POLARITY_MASK BIT(1)
> +#define OC1_CFG_EN_THROTTLE_MASK BIT(0)
> +
> +#define OC1_CNT_THRESHOLD 0x314
> +#define OC1_THROTTLE_PERIOD 0x318
> +#define OC1_ALARM_COUNT 0x31c
> +#define OC1_FILTER 0x320
> +#define OC1_STATS 0x3a8
> +
> #define OC_INTR_STATUS 0x39c
> #define OC_INTR_ENABLE 0x3a0
> #define OC_INTR_DISABLE 0x3a4
> +#define OC_STATS_CTL 0x3c4
> +#define OC_STATS_CTL_CLR_ALL 0x2
> +#define OC_STATS_CTL_EN_ALL 0x1
>
> #define OC_INTR_OC1_MASK BIT(0)
> #define OC_INTR_OC2_MASK BIT(1)
> @@ -207,6 +224,25 @@
> #define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
> (THROT_OFFSET * throt))
>
> +#define ALARM_OFFSET 0x14
> +#define ALARM_CFG(throt) (OC1_CFG + \
> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
> +
> +#define ALARM_CNT_THRESHOLD(throt) (OC1_CNT_THRESHOLD + \
> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
> +
> +#define ALARM_THROTTLE_PERIOD(throt) (OC1_THROTTLE_PERIOD + \
> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
> +
> +#define ALARM_ALARM_COUNT(throt) (OC1_ALARM_COUNT + \
> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
> +
> +#define ALARM_FILTER(throt) (OC1_FILTER + \
> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
> +
> +#define ALARM_STATS(throt) (OC1_STATS + \
> + (4 * (throt - THROTTLE_OC1)))
> +
> /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
> #define CCROC_THROT_OFFSET 0x0c
> #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
> @@ -218,6 +254,9 @@
> #define THERMCTL_LVL_REGS_SIZE 0x20
> #define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
>
> +#define OC_THROTTLE_MODE_DISABLED 0
> +#define OC_THROTTLE_MODE_BRIEF 2
> +
> static const int min_low_temp = -127000;
> static const int max_high_temp = 127000;
>
> @@ -266,6 +305,15 @@ struct tegra_thermctl_zone {
> const struct tegra_tsensor_group *sg;
> };
>
> +struct soctherm_oc_cfg {
> + u32 active_low;
> + u32 throt_period;
> + u32 alarm_cnt_thresh;
> + u32 alarm_filter;
> + u32 mode;
> + bool intr_en;
> +};
> +
> struct soctherm_throt_cfg {
> const char *name;
> unsigned int id;
> @@ -273,6 +321,7 @@ struct soctherm_throt_cfg {
> u8 cpu_throt_level;
> u32 cpu_throt_depth;
> u32 gpu_throt_level;
> + struct soctherm_oc_cfg oc_cfg;
> struct thermal_cooling_device *cdev;
> bool init;
> };
> @@ -715,7 +764,7 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
> return 0;
> }
>
> - for (i = 0; i < THROTTLE_SIZE; i++) {
> + for (i = 0; i < THROTTLE_OC1; i++) {
> struct thermal_cooling_device *cdev;
>
> if (!ts->throt_cfgs[i].init)
> @@ -1537,6 +1586,32 @@ static int soctherm_thermtrips_parse(struct platform_device *pdev)
> return 0;
> }
>
> +static void soctherm_oc_cfg_parse(struct device *dev,
> + struct device_node *np_oc,
> + struct soctherm_throt_cfg *stc)
> +{
> + u32 val;
> +
> + if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
> + stc->oc_cfg.active_low = 1;
> + else
> + stc->oc_cfg.active_low = 0;
> +
> + if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
> + stc->oc_cfg.intr_en = 1;
> + stc->oc_cfg.alarm_cnt_thresh = val;
> + }
> +
> + if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
> + stc->oc_cfg.throt_period = val;
> +
> + if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
> + stc->oc_cfg.alarm_filter = val;
> +
> + /* BRIEF throttling by default, do not support STICKY */
> + stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
> +}
> +
> static int soctherm_throt_cfg_parse(struct device *dev,
> struct device_node *np,
> struct soctherm_throt_cfg *stc)
> @@ -1619,24 +1694,34 @@ static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
> continue;
> }
>
> + if (stc->init) {
> + dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
> + of_node_put(np_stcc);
> + break;
> + }
>
> err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
> if (err)
> continue;
>
> - tcd = thermal_of_cooling_device_register(np_stcc,
> + if (stc->id >= THROTTLE_OC1) {
> + soctherm_oc_cfg_parse(dev, np_stcc, stc);
> + stc->init = true;
> + } else {
> +
> + tcd = thermal_of_cooling_device_register(np_stcc,
> (char *)name, ts,
> &throt_cooling_ops);
> - of_node_put(np_stcc);
> - if (IS_ERR_OR_NULL(tcd)) {
> - dev_err(dev,
> - "throttle-cfg: %s: failed to register cooling device\n",
> - name);
> - continue;
> + if (IS_ERR_OR_NULL(tcd)) {
> + dev_err(dev,
> + "throttle-cfg: %s: failed to register cooling device\n",
> + name);
> + continue;
> + }
> + stc->cdev = tcd;
> + stc->init = true;
> }
>
> - stc->cdev = tcd;
> - stc->init = true;
> }
>
> of_node_put(np_stc);
> @@ -1787,6 +1872,28 @@ static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
> writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
> }
>
> +static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
> + enum soctherm_throttle_id throt)
> +{
> + u32 r;
> + struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
> +
> + if (oc->mode == OC_THROTTLE_MODE_DISABLED)
> + return -EINVAL;
> +
> + r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
> + r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
> + r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
> + r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
> + writel(r, ts->regs + ALARM_CFG(throt));
> + writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
> + writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
> + writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
> + soctherm_oc_intr_enable(ts, throt, oc->intr_en);
> +
> + return 0;
> +}
> +
> /**
> * soctherm_throttle_program() - programs pulse skippers' configuration
> * @throt: the LIGHT/HEAVY of the throttle event id.
> @@ -1803,6 +1910,9 @@ static void soctherm_throttle_program(struct tegra_soctherm *ts,
> if (!stc.init)
> return;
>
> + if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
> + return;
> +
> /* Setup PSKIP parameters */
> if (ts->soc->use_ccroc)
> throttlectl_cpu_level_select(ts, throt);
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 12/12] thermal: tegra: enable OC hw throttle
2019-04-23 15:46 ` Eduardo Valentin
@ 2019-04-24 8:36 ` Wei Ni
2019-04-24 9:49 ` Wei Ni
0 siblings, 1 reply; 18+ messages in thread
From: Wei Ni @ 2019-04-24 8:36 UTC (permalink / raw)
To: Eduardo Valentin
Cc: daniel.lezcano, robh, thierry.reding, linux-tegra, rui.zhang,
srikars, linux-kernel, linux-pm, devicetree
On 23/4/2019 11:46 PM, Eduardo Valentin wrote:
> On Thu, Feb 21, 2019 at 06:18:47PM +0800, Wei Ni wrote:
>> Parse Over Current settings from DT and program them to
>> generate interrupts. Also enable hw throttling whenever
>> there are OC events. Log the OC events as debug messages.
>>
>> Signed-off-by: Wei Ni <wni@nvidia.com>
>
> I applied this series except for this specific patch which:
> a. does not apply clean
> b. does not compile.
>
> Please rebase on top of my -linus branch and resend this. remember to
> checkpatch and compile and boot test before sending.
Thanks for your comment, will rebase and test it.
>
>> ---
>> drivers/thermal/tegra/soctherm.c | 130 ++++++++++++++++++++++++++++++++++++---
>> 1 file changed, 120 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
>> index b8c66368e54e..6e3f329d1ac4 100644
>> --- a/drivers/thermal/tegra/soctherm.c
>> +++ b/drivers/thermal/tegra/soctherm.c
>> @@ -106,9 +106,26 @@
>> #define STATS_CTL_CLR_UP 0x2
>> #define STATS_CTL_EN_UP 0x1
>>
>> +#define OC1_CFG 0x310
>> +#define OC1_CFG_LONG_LATENCY_MASK BIT(6)
>> +#define OC1_CFG_HW_RESTORE_MASK BIT(5)
>> +#define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4)
>> +#define OC1_CFG_THROTTLE_MODE_MASK (0x3 << 2)
>> +#define OC1_CFG_ALARM_POLARITY_MASK BIT(1)
>> +#define OC1_CFG_EN_THROTTLE_MASK BIT(0)
>> +
>> +#define OC1_CNT_THRESHOLD 0x314
>> +#define OC1_THROTTLE_PERIOD 0x318
>> +#define OC1_ALARM_COUNT 0x31c
>> +#define OC1_FILTER 0x320
>> +#define OC1_STATS 0x3a8
>> +
>> #define OC_INTR_STATUS 0x39c
>> #define OC_INTR_ENABLE 0x3a0
>> #define OC_INTR_DISABLE 0x3a4
>> +#define OC_STATS_CTL 0x3c4
>> +#define OC_STATS_CTL_CLR_ALL 0x2
>> +#define OC_STATS_CTL_EN_ALL 0x1
>>
>> #define OC_INTR_OC1_MASK BIT(0)
>> #define OC_INTR_OC2_MASK BIT(1)
>> @@ -207,6 +224,25 @@
>> #define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
>> (THROT_OFFSET * throt))
>>
>> +#define ALARM_OFFSET 0x14
>> +#define ALARM_CFG(throt) (OC1_CFG + \
>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>> +
>> +#define ALARM_CNT_THRESHOLD(throt) (OC1_CNT_THRESHOLD + \
>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>> +
>> +#define ALARM_THROTTLE_PERIOD(throt) (OC1_THROTTLE_PERIOD + \
>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>> +
>> +#define ALARM_ALARM_COUNT(throt) (OC1_ALARM_COUNT + \
>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>> +
>> +#define ALARM_FILTER(throt) (OC1_FILTER + \
>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>> +
>> +#define ALARM_STATS(throt) (OC1_STATS + \
>> + (4 * (throt - THROTTLE_OC1)))
>> +
>> /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
>> #define CCROC_THROT_OFFSET 0x0c
>> #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
>> @@ -218,6 +254,9 @@
>> #define THERMCTL_LVL_REGS_SIZE 0x20
>> #define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
>>
>> +#define OC_THROTTLE_MODE_DISABLED 0
>> +#define OC_THROTTLE_MODE_BRIEF 2
>> +
>> static const int min_low_temp = -127000;
>> static const int max_high_temp = 127000;
>>
>> @@ -266,6 +305,15 @@ struct tegra_thermctl_zone {
>> const struct tegra_tsensor_group *sg;
>> };
>>
>> +struct soctherm_oc_cfg {
>> + u32 active_low;
>> + u32 throt_period;
>> + u32 alarm_cnt_thresh;
>> + u32 alarm_filter;
>> + u32 mode;
>> + bool intr_en;
>> +};
>> +
>> struct soctherm_throt_cfg {
>> const char *name;
>> unsigned int id;
>> @@ -273,6 +321,7 @@ struct soctherm_throt_cfg {
>> u8 cpu_throt_level;
>> u32 cpu_throt_depth;
>> u32 gpu_throt_level;
>> + struct soctherm_oc_cfg oc_cfg;
>> struct thermal_cooling_device *cdev;
>> bool init;
>> };
>> @@ -715,7 +764,7 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
>> return 0;
>> }
>>
>> - for (i = 0; i < THROTTLE_SIZE; i++) {
>> + for (i = 0; i < THROTTLE_OC1; i++) {
>> struct thermal_cooling_device *cdev;
>>
>> if (!ts->throt_cfgs[i].init)
>> @@ -1537,6 +1586,32 @@ static int soctherm_thermtrips_parse(struct platform_device *pdev)
>> return 0;
>> }
>>
>> +static void soctherm_oc_cfg_parse(struct device *dev,
>> + struct device_node *np_oc,
>> + struct soctherm_throt_cfg *stc)
>> +{
>> + u32 val;
>> +
>> + if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
>> + stc->oc_cfg.active_low = 1;
>> + else
>> + stc->oc_cfg.active_low = 0;
>> +
>> + if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
>> + stc->oc_cfg.intr_en = 1;
>> + stc->oc_cfg.alarm_cnt_thresh = val;
>> + }
>> +
>> + if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
>> + stc->oc_cfg.throt_period = val;
>> +
>> + if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
>> + stc->oc_cfg.alarm_filter = val;
>> +
>> + /* BRIEF throttling by default, do not support STICKY */
>> + stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
>> +}
>> +
>> static int soctherm_throt_cfg_parse(struct device *dev,
>> struct device_node *np,
>> struct soctherm_throt_cfg *stc)
>> @@ -1619,24 +1694,34 @@ static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
>> continue;
>> }
>>
>> + if (stc->init) {
>> + dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
>> + of_node_put(np_stcc);
>> + break;
>> + }
>>
>> err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
>> if (err)
>> continue;
>>
>> - tcd = thermal_of_cooling_device_register(np_stcc,
>> + if (stc->id >= THROTTLE_OC1) {
>> + soctherm_oc_cfg_parse(dev, np_stcc, stc);
>> + stc->init = true;
>> + } else {
>> +
>> + tcd = thermal_of_cooling_device_register(np_stcc,
>> (char *)name, ts,
>> &throt_cooling_ops);
>> - of_node_put(np_stcc);
>> - if (IS_ERR_OR_NULL(tcd)) {
>> - dev_err(dev,
>> - "throttle-cfg: %s: failed to register cooling device\n",
>> - name);
>> - continue;
>> + if (IS_ERR_OR_NULL(tcd)) {
>> + dev_err(dev,
>> + "throttle-cfg: %s: failed to register cooling device\n",
>> + name);
>> + continue;
>> + }
>> + stc->cdev = tcd;
>> + stc->init = true;
>> }
>>
>> - stc->cdev = tcd;
>> - stc->init = true;
>> }
>>
>> of_node_put(np_stc);
>> @@ -1787,6 +1872,28 @@ static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
>> writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
>> }
>>
>> +static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
>> + enum soctherm_throttle_id throt)
>> +{
>> + u32 r;
>> + struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
>> +
>> + if (oc->mode == OC_THROTTLE_MODE_DISABLED)
>> + return -EINVAL;
>> +
>> + r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
>> + r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
>> + r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
>> + r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
>> + writel(r, ts->regs + ALARM_CFG(throt));
>> + writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
>> + writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
>> + writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
>> + soctherm_oc_intr_enable(ts, throt, oc->intr_en);
>> +
>> + return 0;
>> +}
>> +
>> /**
>> * soctherm_throttle_program() - programs pulse skippers' configuration
>> * @throt: the LIGHT/HEAVY of the throttle event id.
>> @@ -1803,6 +1910,9 @@ static void soctherm_throttle_program(struct tegra_soctherm *ts,
>> if (!stc.init)
>> return;
>>
>> + if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
>> + return;
>> +
>> /* Setup PSKIP parameters */
>> if (ts->soc->use_ccroc)
>> throttlectl_cpu_level_select(ts, throt);
>> --
>> 2.7.4
>>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 12/12] thermal: tegra: enable OC hw throttle
2019-04-24 8:36 ` Wei Ni
@ 2019-04-24 9:49 ` Wei Ni
0 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-04-24 9:49 UTC (permalink / raw)
To: Eduardo Valentin
Cc: daniel.lezcano, robh, thierry.reding, linux-tegra, rui.zhang,
srikars, linux-kernel, linux-pm, devicetree
Hi Eduardo,
On 24/4/2019 4:36 PM, Wei Ni wrote:
>
>
> On 23/4/2019 11:46 PM, Eduardo Valentin wrote:
>> On Thu, Feb 21, 2019 at 06:18:47PM +0800, Wei Ni wrote:
>>> Parse Over Current settings from DT and program them to
>>> generate interrupts. Also enable hw throttling whenever
>>> there are OC events. Log the OC events as debug messages.
>>>
>>> Signed-off-by: Wei Ni <wni@nvidia.com>
>>
>> I applied this series except for this specific patch which:
>> a. does not apply clean
>> b. does not compile.
>>
>> Please rebase on top of my -linus branch and resend this. remember to
>> checkpatch and compile and boot test before sending.
>
> Thanks for your comment, will rebase and test it.
I git clone your
"git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git",
and "git am" this series, but doesn't have problems, all patches can be
applied one by one.
Because the CONFIG_TEGRA_SOCTHERM didn't be enabled in the defconfig, so
the driver doesn't be compiled. I will send the patch to enable it next.
Did you miss any patches before applying this last one, could you please
try it again?
Thanks.
Wei.
>
>>
>>> ---
>>> drivers/thermal/tegra/soctherm.c | 130 ++++++++++++++++++++++++++++++++++++---
>>> 1 file changed, 120 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
>>> index b8c66368e54e..6e3f329d1ac4 100644
>>> --- a/drivers/thermal/tegra/soctherm.c
>>> +++ b/drivers/thermal/tegra/soctherm.c
>>> @@ -106,9 +106,26 @@
>>> #define STATS_CTL_CLR_UP 0x2
>>> #define STATS_CTL_EN_UP 0x1
>>>
>>> +#define OC1_CFG 0x310
>>> +#define OC1_CFG_LONG_LATENCY_MASK BIT(6)
>>> +#define OC1_CFG_HW_RESTORE_MASK BIT(5)
>>> +#define OC1_CFG_PWR_GOOD_MASK_MASK BIT(4)
>>> +#define OC1_CFG_THROTTLE_MODE_MASK (0x3 << 2)
>>> +#define OC1_CFG_ALARM_POLARITY_MASK BIT(1)
>>> +#define OC1_CFG_EN_THROTTLE_MASK BIT(0)
>>> +
>>> +#define OC1_CNT_THRESHOLD 0x314
>>> +#define OC1_THROTTLE_PERIOD 0x318
>>> +#define OC1_ALARM_COUNT 0x31c
>>> +#define OC1_FILTER 0x320
>>> +#define OC1_STATS 0x3a8
>>> +
>>> #define OC_INTR_STATUS 0x39c
>>> #define OC_INTR_ENABLE 0x3a0
>>> #define OC_INTR_DISABLE 0x3a4
>>> +#define OC_STATS_CTL 0x3c4
>>> +#define OC_STATS_CTL_CLR_ALL 0x2
>>> +#define OC_STATS_CTL_EN_ALL 0x1
>>>
>>> #define OC_INTR_OC1_MASK BIT(0)
>>> #define OC_INTR_OC2_MASK BIT(1)
>>> @@ -207,6 +224,25 @@
>>> #define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
>>> (THROT_OFFSET * throt))
>>>
>>> +#define ALARM_OFFSET 0x14
>>> +#define ALARM_CFG(throt) (OC1_CFG + \
>>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>>> +
>>> +#define ALARM_CNT_THRESHOLD(throt) (OC1_CNT_THRESHOLD + \
>>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>>> +
>>> +#define ALARM_THROTTLE_PERIOD(throt) (OC1_THROTTLE_PERIOD + \
>>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>>> +
>>> +#define ALARM_ALARM_COUNT(throt) (OC1_ALARM_COUNT + \
>>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>>> +
>>> +#define ALARM_FILTER(throt) (OC1_FILTER + \
>>> + (ALARM_OFFSET * (throt - THROTTLE_OC1)))
>>> +
>>> +#define ALARM_STATS(throt) (OC1_STATS + \
>>> + (4 * (throt - THROTTLE_OC1)))
>>> +
>>> /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
>>> #define CCROC_THROT_OFFSET 0x0c
>>> #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
>>> @@ -218,6 +254,9 @@
>>> #define THERMCTL_LVL_REGS_SIZE 0x20
>>> #define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
>>>
>>> +#define OC_THROTTLE_MODE_DISABLED 0
>>> +#define OC_THROTTLE_MODE_BRIEF 2
>>> +
>>> static const int min_low_temp = -127000;
>>> static const int max_high_temp = 127000;
>>>
>>> @@ -266,6 +305,15 @@ struct tegra_thermctl_zone {
>>> const struct tegra_tsensor_group *sg;
>>> };
>>>
>>> +struct soctherm_oc_cfg {
>>> + u32 active_low;
>>> + u32 throt_period;
>>> + u32 alarm_cnt_thresh;
>>> + u32 alarm_filter;
>>> + u32 mode;
>>> + bool intr_en;
>>> +};
>>> +
>>> struct soctherm_throt_cfg {
>>> const char *name;
>>> unsigned int id;
>>> @@ -273,6 +321,7 @@ struct soctherm_throt_cfg {
>>> u8 cpu_throt_level;
>>> u32 cpu_throt_depth;
>>> u32 gpu_throt_level;
>>> + struct soctherm_oc_cfg oc_cfg;
>>> struct thermal_cooling_device *cdev;
>>> bool init;
>>> };
>>> @@ -715,7 +764,7 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
>>> return 0;
>>> }
>>>
>>> - for (i = 0; i < THROTTLE_SIZE; i++) {
>>> + for (i = 0; i < THROTTLE_OC1; i++) {
>>> struct thermal_cooling_device *cdev;
>>>
>>> if (!ts->throt_cfgs[i].init)
>>> @@ -1537,6 +1586,32 @@ static int soctherm_thermtrips_parse(struct platform_device *pdev)
>>> return 0;
>>> }
>>>
>>> +static void soctherm_oc_cfg_parse(struct device *dev,
>>> + struct device_node *np_oc,
>>> + struct soctherm_throt_cfg *stc)
>>> +{
>>> + u32 val;
>>> +
>>> + if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
>>> + stc->oc_cfg.active_low = 1;
>>> + else
>>> + stc->oc_cfg.active_low = 0;
>>> +
>>> + if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
>>> + stc->oc_cfg.intr_en = 1;
>>> + stc->oc_cfg.alarm_cnt_thresh = val;
>>> + }
>>> +
>>> + if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
>>> + stc->oc_cfg.throt_period = val;
>>> +
>>> + if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
>>> + stc->oc_cfg.alarm_filter = val;
>>> +
>>> + /* BRIEF throttling by default, do not support STICKY */
>>> + stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
>>> +}
>>> +
>>> static int soctherm_throt_cfg_parse(struct device *dev,
>>> struct device_node *np,
>>> struct soctherm_throt_cfg *stc)
>>> @@ -1619,24 +1694,34 @@ static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
>>> continue;
>>> }
>>>
>>> + if (stc->init) {
>>> + dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
>>> + of_node_put(np_stcc);
>>> + break;
>>> + }
>>>
>>> err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
>>> if (err)
>>> continue;
>>>
>>> - tcd = thermal_of_cooling_device_register(np_stcc,
>>> + if (stc->id >= THROTTLE_OC1) {
>>> + soctherm_oc_cfg_parse(dev, np_stcc, stc);
>>> + stc->init = true;
>>> + } else {
>>> +
>>> + tcd = thermal_of_cooling_device_register(np_stcc,
>>> (char *)name, ts,
>>> &throt_cooling_ops);
>>> - of_node_put(np_stcc);
>>> - if (IS_ERR_OR_NULL(tcd)) {
>>> - dev_err(dev,
>>> - "throttle-cfg: %s: failed to register cooling device\n",
>>> - name);
>>> - continue;
>>> + if (IS_ERR_OR_NULL(tcd)) {
>>> + dev_err(dev,
>>> + "throttle-cfg: %s: failed to register cooling device\n",
>>> + name);
>>> + continue;
>>> + }
>>> + stc->cdev = tcd;
>>> + stc->init = true;
>>> }
>>>
>>> - stc->cdev = tcd;
>>> - stc->init = true;
>>> }
>>>
>>> of_node_put(np_stc);
>>> @@ -1787,6 +1872,28 @@ static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
>>> writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
>>> }
>>>
>>> +static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
>>> + enum soctherm_throttle_id throt)
>>> +{
>>> + u32 r;
>>> + struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
>>> +
>>> + if (oc->mode == OC_THROTTLE_MODE_DISABLED)
>>> + return -EINVAL;
>>> +
>>> + r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
>>> + r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
>>> + r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
>>> + r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
>>> + writel(r, ts->regs + ALARM_CFG(throt));
>>> + writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
>>> + writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
>>> + writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
>>> + soctherm_oc_intr_enable(ts, throt, oc->intr_en);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> /**
>>> * soctherm_throttle_program() - programs pulse skippers' configuration
>>> * @throt: the LIGHT/HEAVY of the throttle event id.
>>> @@ -1803,6 +1910,9 @@ static void soctherm_throttle_program(struct tegra_soctherm *ts,
>>> if (!stc.init)
>>> return;
>>>
>>> + if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
>>> + return;
>>> +
>>> /* Setup PSKIP parameters */
>>> if (ts->soc->use_ccroc)
>>> throttlectl_cpu_level_select(ts, throt);
>>> --
>>> 2.7.4
>>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 00/12] Add some functionalities for Tegra soctherm
2019-02-21 10:18 [PATCH v2 00/12] Add some functionalities for Tegra soctherm Wei Ni
` (11 preceding siblings ...)
2019-02-21 10:18 ` [PATCH v2 12/12] thermal: tegra: enable OC hw throttle Wei Ni
@ 2019-03-26 2:17 ` Wei Ni
12 siblings, 0 replies; 18+ messages in thread
From: Wei Ni @ 2019-03-26 2:17 UTC (permalink / raw)
To: daniel.lezcano, edubezval, robh
Cc: thierry.reding, linux-tegra, rui.zhang, srikars, linux-kernel,
linux-pm, devicetree
Hi all,
Does there have any comments on this serial?
Thanks.
Wei.
On 21/2/2019 6:18 PM, Wei Ni wrote:
> Move the hw/sw shutdown patches into this serial. There already have
> some discussion for it in https://lkml.org/lkml/2018/12/7/225.
> Support GPU HW throttle, thermal IRQ, set_trips(), EDP IRQ and OC
> hw throttle.
>
> Main change from v1:
> 1. Use boolean for "nvidia,polarity-active-low".
> 2. Add suffix "-us" for "nvidia,throttle-period".
>
>
> Wei Ni (12):
> of: Add bindings of thermtrip for Tegra soctherm
> thermal: tegra: support hw and sw shutdown
> arm64: dts: tegra210: set thermtrip
> of: Add bindings of gpu hw throttle for Tegra soctherm
> thermal: tegra: add support for gpu hw-throttle
> arm64: dts: tegra210: set gpu hw throttle level
> thermal: tegra: add support for thermal IRQ
> thermal: tegra: add set_trips functionality
> thermal: tegra: add support for EDP IRQ
> arm64: dts: tegra210: set EDP interrupt line
> of: Add bindings of OC hw throttle for Tegra soctherm
> thermal: tegra: enable OC hw throttle
>
> .../bindings/thermal/nvidia,tegra124-soctherm.txt | 62 +-
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 20 +-
> drivers/thermal/tegra/soctherm.c | 961 +++++++++++++++++++--
> drivers/thermal/tegra/soctherm.h | 16 +
> drivers/thermal/tegra/tegra124-soctherm.c | 7 +-
> drivers/thermal/tegra/tegra132-soctherm.c | 7 +-
> drivers/thermal/tegra/tegra210-soctherm.c | 15 +-
> include/dt-bindings/thermal/tegra124-soctherm.h | 8 +-
> 8 files changed, 1020 insertions(+), 76 deletions(-)
>
^ permalink raw reply [flat|nested] 18+ messages in thread