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> > > > > > > Looking at my copy of L4T r21, the EMC count_weight should be 256 on Te= gra114, while it is 4*256 on Tegra124, so different SoC data should be used= . (I haven't checked if anything else is different) > > >=20 > You are correct, tegra114 seems to use 1 EMC clock per transaction. I > will move and expand comment from tegra124 entry regarding > count_weight to include info about all 3 supported entries if you > don't mind. >=20 > I have a question regarding tegra_devfreq_device_config to be used > with tegra114. From tegratab kernel I have, existing > tegra124_device_configs configuration seems to fit tegra114, may you > confirm this? Or, if L4T r21 you use, uses different values, may you > provide those to fill up tegra_devfreq_device_config for tegra114. Can confirm the offset and irq mask are the same. The coefficients are a bi= t different in the L4T tree but they don't match the upstream tegra124 valu= es either so I guess that's fine. Here's the exact values: static struct actmon_dev actmon_dev_emc =3D { .reg =3D 0x1c0, .glb_status_irq_mask =3D (0x1 << 26), .dev_id =3D "tegra_actmon", .con_id =3D "emc", /* EMC suspend floor to guarantee suspend entry on PLLM */ .suspend_freq =3D EMC_PLLP_FREQ_MAX + 2000, .boost_freq_step =3D 16000, .boost_up_coef =3D 200, .boost_down_coef =3D 50, #if (defined(CONFIG_ARCH_TEGRA_14x_SOC) || \ defined(CONFIG_ARCH_TEGRA_12x_SOC) || \ defined(CONFIG_ARCH_TEGRA_13x_SOC)) .boost_up_threshold =3D 70, .boost_down_threshold =3D 50, #else .boost_up_threshold =3D 60, .boost_down_threshold =3D 40, #endif .up_wmark_window =3D 1, .down_wmark_window =3D 3, .avg_window_log2 =3D ACTMON_DEFAULT_AVG_WINDOW_LOG2, #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC) .count_weight =3D 0x200, #elif defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_S= OC) .count_weight =3D 0x400, #else .count_weight =3D 0x100, #endif .type =3D ACTMON_FREQ_SAMPLER, .state =3D ACTMON_UNINITIALIZED, .rate_change_nb =3D { .notifier_call =3D actmon_rate_notify_cb, }, }; #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC= ) #define CPU_AVG_ACT_THRESHOLD 2000 #else #define CPU_AVG_ACT_THRESHOLD 50000 #endif /* EMC-cpu activity monitor: frequency sampling device: * activity counter is incremented every 256 memory transactions, and * each transaction takes 2 EMC clocks; count_weight =3D 512 on Tegra3. * On Tegra11 there is only 1 clock per transaction, hence weight =3D 256. */ static struct actmon_dev actmon_dev_cpu_emc =3D { .reg =3D 0x200, .glb_status_irq_mask =3D (0x1 << 25), .dev_id =3D "tegra_mon", .con_id =3D "cpu_emc", .boost_freq_step =3D 16000, .boost_up_coef =3D 800, .boost_down_coef =3D 90, .boost_up_threshold =3D 27, .boost_down_threshold =3D 10, .avg_dependency_threshold =3D CPU_AVG_ACT_THRESHOLD, .up_wmark_window =3D 1, .down_wmark_window =3D 3, .avg_window_log2 =3D ACTMON_DEFAULT_AVG_WINDOW_LOG2, #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC) .count_weight =3D 0x200, #elif defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_S= OC) .count_weight =3D 0x400, #else .count_weight =3D 0x100, #endif .type =3D ACTMON_FREQ_SAMPLER, .state =3D ACTMON_UNINITIALIZED, .rate_change_nb =3D { .notifier_call =3D actmon_rate_notify_cb, }, }; >=20 > > Cheers, > > Mikko > > > >