From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ley Foon Tan Subject: [PATCH v5 3/3] dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 Date: Tue, 26 Feb 2019 17:15:48 +0800 Message-ID: <1551172548-36344-4-git-send-email-ley.foon.tan@intel.com> References: <1551172548-36344-1-git-send-email-ley.foon.tan@intel.com> Return-path: In-Reply-To: <1551172548-36344-1-git-send-email-ley.foon.tan@intel.com> Sender: linux-kernel-owner@vger.kernel.org To: Bjorn Helgaas , Lorenzo Pieralisi Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, lftan.linux@gmail.com, Ley Foon Tan List-Id: devicetree@vger.kernel.org Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/altera-pcie.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f17c91a..816b244a221e 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 2.19.0