* [PATCH v4 0/7] scsi: ufs-mediatek: Add ufshci and ufsphy support for Mediatek SoC chips
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
2019-03-13 4:10 ` [PATCH v4 1/7] scsi: ufs: Introduce ufshcd_get_pwr_dev_param Stanley Chu
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
Hello,
This patch series adds UFS M-PHY and UFS host driver support in MediaTek chipsets.
In the meantime, re-factors ufshcd_get_pwr_dev_param in vendors' drivers. This function is for vendors to decide finally agreed attributes for power mode change if vendors define
their host capability in struct ufs_dev_params. Because it is using by both ufs-qcom and ufs-hisi and also used in ufs-mediatek in this serious, simply re-factor it and then every vendors can reuse it.
Changes since v3:
- dt-bindings: Use specific compatible name for both ufs-mediatek and phy-mtk-ufs, remove interrupt-parent and lanes-per-direction in ufs-mediatek, and fix descriptions.
Changes since v2:
- Fix header style with SPDX-License-Identifier declaration used.
- Simplify ufs-phy-mtk to single source file since we has one MPHY version now, and do fixes according to Chunfeng Yun's comments.
- Add dt-bindings of ufs-phy-mtk.
Changes since v1:
- Re-factor ufshcd_get_pwr_dev_param in mediatek/qcom/hisi vendor drivers.
- Introduce ufs-phy-mtk to have a good extension capability for different power control flows in future different MPHY versions.
- Bind ufs-phy-mtk and hook suitable callbacks in ufs-mediatek driver.
- Use PA_LOCAL_TX_LCC_ENABLE attribute defined in unipro.h instead.
- Do some minor format fixes.
Stanley Chu (7):
scsi: ufs: Introduce ufshcd_get_pwr_dev_param
scsi: ufs-qcom: Re-factor ufshcd_get_pwr_dev_param
scsi: ufs-hisi: Re-factor ufshcd_get_pwr_dev_param
dt-bindings: phy: Add document for phy-mtk-ufs
dt-bindings: scsi: ufs: Add document for ufs-mediatek
phy: mediatek: Add UFS M-PHY driver
scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips
.../devicetree/bindings/phy/phy-mtk-ufs.txt | 36 ++
.../devicetree/bindings/ufs/ufs-mediatek.txt | 44 +++
drivers/phy/mediatek/Kconfig | 9 +
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-ufs.c | 239 ++++++++++++
drivers/scsi/ufs/Kconfig | 14 +
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-hisi.c | 109 +-----
drivers/scsi/ufs/ufs-mediatek.c | 368 ++++++++++++++++++
drivers/scsi/ufs/ufs-mediatek.h | 54 +++
drivers/scsi/ufs/ufs-qcom.c | 106 +----
drivers/scsi/ufs/ufshcd-pltfrm.c | 98 +++++
drivers/scsi/ufs/ufshcd-pltfrm.h | 21 +
13 files changed, 893 insertions(+), 207 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
create mode 100644 drivers/phy/mediatek/phy-mtk-ufs.c
create mode 100644 drivers/scsi/ufs/ufs-mediatek.c
create mode 100644 drivers/scsi/ufs/ufs-mediatek.h
--
2.18.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v4 1/7] scsi: ufs: Introduce ufshcd_get_pwr_dev_param
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
2019-03-13 4:10 ` [PATCH v4 0/7] scsi: ufs-mediatek: Add ufshci and ufsphy " Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
2019-03-13 4:10 ` [PATCH v4 2/7] scsi: ufs-qcom: Re-factor ufshcd_get_pwr_dev_param Stanley Chu
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
ufshcd_get_pwr_dev_param is for vendors to decide finally
agreed attributes for power mode change if vendors define
their host capability in struct ufs_dev_params.
This api is using by both ufs-qcom and ufs-hisi now. Simply
re-factor it and then every vendors can reuse it.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
---
drivers/scsi/ufs/ufshcd-pltfrm.c | 98 ++++++++++++++++++++++++++++++++
drivers/scsi/ufs/ufshcd-pltfrm.h | 21 +++++++
2 files changed, 119 insertions(+)
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
index 895a9b5ac989..508c561c9a62 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
@@ -39,6 +39,7 @@
#include "ufshcd.h"
#include "ufshcd-pltfrm.h"
+#include "unipro.h"
#define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2
@@ -289,6 +290,103 @@ static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
}
}
+/**
+ * ufshcd_get_pwr_dev_param - get finally agreed attributes for
+ * power mode change
+ * @pltfrm_param: pointer to platform parameters
+ * @dev_max: pointer to device attributes
+ * @agreed_pwr: returned agreed attributes
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+int ufshcd_get_pwr_dev_param(struct ufs_dev_params *pltfrm_param,
+ struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr)
+{
+ int min_pltfrm_gear;
+ int min_dev_gear;
+ bool is_dev_sup_hs = false;
+ bool is_pltfrm_max_hs = false;
+
+ if (dev_max->pwr_rx == FAST_MODE)
+ is_dev_sup_hs = true;
+
+ if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
+ is_pltfrm_max_hs = true;
+ min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
+ pltfrm_param->hs_tx_gear);
+ } else {
+ min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
+ pltfrm_param->pwm_tx_gear);
+ }
+
+ /*
+ * device doesn't support HS but
+ * pltfrm_param->desired_working_mode is HS,
+ * thus device and pltfrm_param don't agree
+ */
+ if (!is_dev_sup_hs && is_pltfrm_max_hs) {
+ pr_info("%s: device doesn't support HS\n",
+ __func__);
+ return -ENOTSUPP;
+ } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
+ /*
+ * since device supports HS, it supports FAST_MODE.
+ * since pltfrm_param->desired_working_mode is also HS
+ * then final decision (FAST/FASTAUTO) is done according
+ * to pltfrm_params as it is the restricting factor
+ */
+ agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
+ agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
+ } else {
+ /*
+ * here pltfrm_param->desired_working_mode is PWM.
+ * it doesn't matter whether device supports HS or PWM,
+ * in both cases pltfrm_param->desired_working_mode will
+ * determine the mode
+ */
+ agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
+ agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
+ }
+
+ /*
+ * we would like tx to work in the minimum number of lanes
+ * between device capability and vendor preferences.
+ * the same decision will be made for rx
+ */
+ agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
+ pltfrm_param->tx_lanes);
+ agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
+ pltfrm_param->rx_lanes);
+
+ /* device maximum gear is the minimum between device rx and tx gears */
+ min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
+
+ /*
+ * if both device capabilities and vendor pre-defined preferences are
+ * both HS or both PWM then set the minimum gear to be the chosen
+ * working gear.
+ * if one is PWM and one is HS then the one that is PWM get to decide
+ * what is the gear, as it is the one that also decided previously what
+ * pwr the device will be configured to.
+ */
+ if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
+ (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
+ agreed_pwr->gear_rx =
+ min_t(u32, min_dev_gear, min_pltfrm_gear);
+ } else if (!is_dev_sup_hs) {
+ agreed_pwr->gear_rx = min_dev_gear;
+ } else {
+ agreed_pwr->gear_rx = min_pltfrm_gear;
+ }
+ agreed_pwr->gear_tx = agreed_pwr->gear_rx;
+
+ agreed_pwr->hs_rate = pltfrm_param->hs_rate;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
+
/**
* ufshcd_pltfrm_init - probe routine of the driver
* @pdev: pointer to Platform device handle
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.h b/drivers/scsi/ufs/ufshcd-pltfrm.h
index df64c4180340..d3ba62269be6 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.h
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.h
@@ -16,6 +16,27 @@
#include "ufshcd.h"
+#define UFS_PWM_MODE 1
+#define UFS_HS_MODE 2
+
+struct ufs_dev_params {
+ u32 pwm_rx_gear; /* pwm rx gear to work in */
+ u32 pwm_tx_gear; /* pwm tx gear to work in */
+ u32 hs_rx_gear; /* hs rx gear to work in */
+ u32 hs_tx_gear; /* hs tx gear to work in */
+ u32 rx_lanes; /* number of rx lanes */
+ u32 tx_lanes; /* number of tx lanes */
+ u32 rx_pwr_pwm; /* rx pwm working pwr */
+ u32 tx_pwr_pwm; /* tx pwm working pwr */
+ u32 rx_pwr_hs; /* rx hs working pwr */
+ u32 tx_pwr_hs; /* tx hs working pwr */
+ u32 hs_rate; /* rate A/B to work in HS */
+ u32 desired_working_mode;
+};
+
+int ufshcd_get_pwr_dev_param(struct ufs_dev_params *dev_param,
+ struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr);
int ufshcd_pltfrm_init(struct platform_device *pdev,
struct ufs_hba_variant_ops *vops);
void ufshcd_pltfrm_shutdown(struct platform_device *pdev);
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v4 2/7] scsi: ufs-qcom: Re-factor ufshcd_get_pwr_dev_param
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
2019-03-13 4:10 ` [PATCH v4 0/7] scsi: ufs-mediatek: Add ufshci and ufsphy " Stanley Chu
2019-03-13 4:10 ` [PATCH v4 1/7] scsi: ufs: Introduce ufshcd_get_pwr_dev_param Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
2019-03-13 4:10 ` [PATCH v4 3/7] scsi: ufs-hisi: " Stanley Chu
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
ufshcd_get_pwr_dev_param function and ufs_dev_params struct
are re-factored to ufs common driver thus change the way this
driver used.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
---
drivers/scsi/ufs/ufs-qcom.c | 106 ++----------------------------------
1 file changed, 4 insertions(+), 102 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 3aeadb14aae1..a6b6f6eb9061 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -595,104 +595,6 @@ static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
return err;
}
-struct ufs_qcom_dev_params {
- u32 pwm_rx_gear; /* pwm rx gear to work in */
- u32 pwm_tx_gear; /* pwm tx gear to work in */
- u32 hs_rx_gear; /* hs rx gear to work in */
- u32 hs_tx_gear; /* hs tx gear to work in */
- u32 rx_lanes; /* number of rx lanes */
- u32 tx_lanes; /* number of tx lanes */
- u32 rx_pwr_pwm; /* rx pwm working pwr */
- u32 tx_pwr_pwm; /* tx pwm working pwr */
- u32 rx_pwr_hs; /* rx hs working pwr */
- u32 tx_pwr_hs; /* tx hs working pwr */
- u32 hs_rate; /* rate A/B to work in HS */
- u32 desired_working_mode;
-};
-
-static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
- struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr)
-{
- int min_qcom_gear;
- int min_dev_gear;
- bool is_dev_sup_hs = false;
- bool is_qcom_max_hs = false;
-
- if (dev_max->pwr_rx == FAST_MODE)
- is_dev_sup_hs = true;
-
- if (qcom_param->desired_working_mode == FAST) {
- is_qcom_max_hs = true;
- min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
- qcom_param->hs_tx_gear);
- } else {
- min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
- qcom_param->pwm_tx_gear);
- }
-
- /*
- * device doesn't support HS but qcom_param->desired_working_mode is
- * HS, thus device and qcom_param don't agree
- */
- if (!is_dev_sup_hs && is_qcom_max_hs) {
- pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
- __func__);
- return -ENOTSUPP;
- } else if (is_dev_sup_hs && is_qcom_max_hs) {
- /*
- * since device supports HS, it supports FAST_MODE.
- * since qcom_param->desired_working_mode is also HS
- * then final decision (FAST/FASTAUTO) is done according
- * to qcom_params as it is the restricting factor
- */
- agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
- qcom_param->rx_pwr_hs;
- } else {
- /*
- * here qcom_param->desired_working_mode is PWM.
- * it doesn't matter whether device supports HS or PWM,
- * in both cases qcom_param->desired_working_mode will
- * determine the mode
- */
- agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
- qcom_param->rx_pwr_pwm;
- }
-
- /*
- * we would like tx to work in the minimum number of lanes
- * between device capability and vendor preferences.
- * the same decision will be made for rx
- */
- agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
- qcom_param->tx_lanes);
- agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
- qcom_param->rx_lanes);
-
- /* device maximum gear is the minimum between device rx and tx gears */
- min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
-
- /*
- * if both device capabilities and vendor pre-defined preferences are
- * both HS or both PWM then set the minimum gear to be the chosen
- * working gear.
- * if one is PWM and one is HS then the one that is PWM get to decide
- * what is the gear, as it is the one that also decided previously what
- * pwr the device will be configured to.
- */
- if ((is_dev_sup_hs && is_qcom_max_hs) ||
- (!is_dev_sup_hs && !is_qcom_max_hs))
- agreed_pwr->gear_rx = agreed_pwr->gear_tx =
- min_t(u32, min_dev_gear, min_qcom_gear);
- else if (!is_dev_sup_hs)
- agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
- else
- agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
-
- agreed_pwr->hs_rate = qcom_param->hs_rate;
- return 0;
-}
-
#ifdef CONFIG_MSM_BUS_SCALING
static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
const char *speed_mode)
@@ -920,7 +822,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
{
u32 val;
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
- struct ufs_qcom_dev_params ufs_qcom_cap;
+ struct ufs_dev_params ufs_qcom_cap;
int ret = 0;
if (!dev_req_params) {
@@ -959,9 +861,9 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
}
- ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
- dev_max_params,
- dev_req_params);
+ ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
+ dev_max_params,
+ dev_req_params);
if (ret) {
pr_err("%s: failed to determine capabilities\n",
__func__);
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v4 3/7] scsi: ufs-hisi: Re-factor ufshcd_get_pwr_dev_param
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
` (2 preceding siblings ...)
2019-03-13 4:10 ` [PATCH v4 2/7] scsi: ufs-qcom: Re-factor ufshcd_get_pwr_dev_param Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
2019-03-13 4:10 ` [PATCH v4 4/7] dt-bindings: phy: Add document for phy-mtk-ufs Stanley Chu
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
ufshcd_get_pwr_dev_param function and ufs_dev_params struct
are re-factored to ufs common driver thus change the way this
driver used.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
---
drivers/scsi/ufs/ufs-hisi.c | 109 ++----------------------------------
1 file changed, 4 insertions(+), 105 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c
index 452e19f8fb47..01faad26ec26 100644
--- a/drivers/scsi/ufs/ufs-hisi.c
+++ b/drivers/scsi/ufs/ufs-hisi.c
@@ -272,108 +272,7 @@ static int ufs_hi3660_link_startup_notify(struct ufs_hba *hba,
return err;
}
-struct ufs_hisi_dev_params {
- u32 pwm_rx_gear; /* pwm rx gear to work in */
- u32 pwm_tx_gear; /* pwm tx gear to work in */
- u32 hs_rx_gear; /* hs rx gear to work in */
- u32 hs_tx_gear; /* hs tx gear to work in */
- u32 rx_lanes; /* number of rx lanes */
- u32 tx_lanes; /* number of tx lanes */
- u32 rx_pwr_pwm; /* rx pwm working pwr */
- u32 tx_pwr_pwm; /* tx pwm working pwr */
- u32 rx_pwr_hs; /* rx hs working pwr */
- u32 tx_pwr_hs; /* tx hs working pwr */
- u32 hs_rate; /* rate A/B to work in HS */
- u32 desired_working_mode;
-};
-
-static int ufs_hisi_get_pwr_dev_param(
- struct ufs_hisi_dev_params *hisi_param,
- struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr)
-{
- int min_hisi_gear;
- int min_dev_gear;
- bool is_dev_sup_hs = false;
- bool is_hisi_max_hs = false;
-
- if (dev_max->pwr_rx == FASTAUTO_MODE || dev_max->pwr_rx == FAST_MODE)
- is_dev_sup_hs = true;
-
- if (hisi_param->desired_working_mode == FAST) {
- is_hisi_max_hs = true;
- min_hisi_gear = min_t(u32, hisi_param->hs_rx_gear,
- hisi_param->hs_tx_gear);
- } else {
- min_hisi_gear = min_t(u32, hisi_param->pwm_rx_gear,
- hisi_param->pwm_tx_gear);
- }
-
- /*
- * device doesn't support HS but
- * hisi_param->desired_working_mode is HS,
- * thus device and hisi_param don't agree
- */
- if (!is_dev_sup_hs && is_hisi_max_hs) {
- pr_err("%s: device not support HS\n", __func__);
- return -ENOTSUPP;
- } else if (is_dev_sup_hs && is_hisi_max_hs) {
- /*
- * since device supports HS, it supports FAST_MODE.
- * since hisi_param->desired_working_mode is also HS
- * then final decision (FAST/FASTAUTO) is done according
- * to hisi_params as it is the restricting factor
- */
- agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
- hisi_param->rx_pwr_hs;
- } else {
- /*
- * here hisi_param->desired_working_mode is PWM.
- * it doesn't matter whether device supports HS or PWM,
- * in both cases hisi_param->desired_working_mode will
- * determine the mode
- */
- agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
- hisi_param->rx_pwr_pwm;
- }
-
- /*
- * we would like tx to work in the minimum number of lanes
- * between device capability and vendor preferences.
- * the same decision will be made for rx
- */
- agreed_pwr->lane_tx =
- min_t(u32, dev_max->lane_tx, hisi_param->tx_lanes);
- agreed_pwr->lane_rx =
- min_t(u32, dev_max->lane_rx, hisi_param->rx_lanes);
-
- /* device maximum gear is the minimum between device rx and tx gears */
- min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
-
- /*
- * if both device capabilities and vendor pre-defined preferences are
- * both HS or both PWM then set the minimum gear to be the chosen
- * working gear.
- * if one is PWM and one is HS then the one that is PWM get to decide
- * what is the gear, as it is the one that also decided previously what
- * pwr the device will be configured to.
- */
- if ((is_dev_sup_hs && is_hisi_max_hs) ||
- (!is_dev_sup_hs && !is_hisi_max_hs))
- agreed_pwr->gear_rx = agreed_pwr->gear_tx =
- min_t(u32, min_dev_gear, min_hisi_gear);
- else
- agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_hisi_gear;
-
- agreed_pwr->hs_rate = hisi_param->hs_rate;
-
- pr_info("ufs final power mode: gear = %d, lane = %d, pwr = %d, rate = %d\n",
- agreed_pwr->gear_rx, agreed_pwr->lane_rx, agreed_pwr->pwr_rx,
- agreed_pwr->hs_rate);
- return 0;
-}
-
-static void ufs_hisi_set_dev_cap(struct ufs_hisi_dev_params *hisi_param)
+static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
{
hisi_param->rx_lanes = UFS_HISI_LIMIT_NUM_LANES_RX;
hisi_param->tx_lanes = UFS_HISI_LIMIT_NUM_LANES_TX;
@@ -434,7 +333,7 @@ static int ufs_hi3660_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
{
- struct ufs_hisi_dev_params ufs_hisi_cap;
+ struct ufs_dev_params ufs_hisi_cap;
int ret = 0;
if (!dev_req_params) {
@@ -447,8 +346,8 @@ static int ufs_hi3660_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
ufs_hisi_set_dev_cap(&ufs_hisi_cap);
- ret = ufs_hisi_get_pwr_dev_param(
- &ufs_hisi_cap, dev_max_params, dev_req_params);
+ ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
+ dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev,
"%s: failed to determine capabilities\n", __func__);
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v4 4/7] dt-bindings: phy: Add document for phy-mtk-ufs
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
` (3 preceding siblings ...)
2019-03-13 4:10 ` [PATCH v4 3/7] scsi: ufs-hisi: " Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
2019-03-13 4:10 ` [PATCH v4 5/7] dt-bindings: scsi: ufs: Add document for ufs-mediatek Stanley Chu
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
Add UFS M-PHY node document for MediaTek SoC chips.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
.../devicetree/bindings/phy/phy-mtk-ufs.txt | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt b/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
new file mode 100644
index 000000000000..dc6c9933b08d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mtk-ufs.txt
@@ -0,0 +1,36 @@
+MediaTek Universal Flash Storage (UFS) M-PHY binding
+--------------------------------------------------------
+
+UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
+Each UFS M-PHY node should have its own node.
+
+To bind UFS M-PHY with UFS host controller, the controller node should
+contain a phandle reference to UFS M-PHY node.
+
+Required properties for UFS M-PHY nodes:
+- compatible : Compatible list, contains the following controller:
+ "mediatek,mt8183-ufsphy" for ufs phy
+ persent on MT81xx chipsets.
+- reg : Address and length of the UFS M-PHY register set.
+- #phy-cells : This property shall be set to 0
+- clocks : List of phandle and clock specifier pairs.
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property. "unipro-clk" and
+ "mp-clk" are mandatory.
+
+Example:
+
+ ufsphy: phy@11fa0000 {
+ compatible = "mediatek,mt8183-ufsphy";
+ reg = <0 0x11fa0000 0 0xc000>;
+ #phy-cells = <0>;
+
+ clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
+ <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>;
+ clock-names = "unipro-clk", "mp-clk";
+ };
+
+ ufshci@11270000 {
+ ...
+ phys = <&ufsphy>;
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v4 5/7] dt-bindings: scsi: ufs: Add document for ufs-mediatek
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
` (4 preceding siblings ...)
2019-03-13 4:10 ` [PATCH v4 4/7] dt-bindings: phy: Add document for phy-mtk-ufs Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
2019-03-13 4:10 ` [PATCH v4 6/7] phy: mediatek: Add UFS M-PHY driver Stanley Chu
2019-03-13 4:10 ` [PATCH v4 7/7] scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
Add UFS and UFS PHY node document for Mediatek SoC chips.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
.../devicetree/bindings/ufs/ufs-mediatek.txt | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
diff --git a/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt b/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
new file mode 100644
index 000000000000..9594e1cd7ecf
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufs-mediatek.txt
@@ -0,0 +1,44 @@
+* Mediatek Universal Flash Storage (UFS) Host Controller
+
+UFS nodes are defined to describe on-chip UFS hardware macro.
+Each UFS Host Controller should have its own node.
+
+To bind UFS PHY with UFS host controller, the controller node should
+contain a phandle reference to UFS M-PHY node.
+
+Required properties for UFS nodes:
+- compatible : Compatible list, contains the following controller:
+ "mediatek,mt8183-ufshci" for MediaTek UFS host controller
+ present on MT81xx chipsets.
+- reg : Address and length of the UFS register set.
+- phys : phandle to m-phy.
+- clocks : List of phandle and clock specifier pairs.
+- clock-names : List of clock input name strings sorted in the same
+ order as the clocks property. "ufs-clk" is mandatory.
+- freq-table-hz : Array of <min max> operating frequencies stored in the same
+ order as the clocks property. If this property is not
+ defined or a value in the array is "0" then it is assumed
+ that the frequency is set by the parent clock or a
+ fixed rate clock source.
+- vcc-supply : Power to the UFS device.
+- vcc-fixed-regulator: Specify that vcc-supply is a fixed regulator.
+
+Example:
+
+ ufsphy: phy@11fa0000 {
+ ...
+ };
+
+ ufshci@11270000 {
+ compatible = "mediatek,mt8183-ufshci";
+ reg = <0 0x11270000 0 0x2300>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&ufsphy>;
+
+ clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>;
+ clock-names = "ufs-clk";
+ freq-table-hz = <0 0>;
+
+ vcc-supply = <&mt_pmic_vemc_ldo_reg>;
+ vcc-fixed-regulator;
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v4 6/7] phy: mediatek: Add UFS M-PHY driver
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
` (5 preceding siblings ...)
2019-03-13 4:10 ` [PATCH v4 5/7] dt-bindings: scsi: ufs: Add document for ufs-mediatek Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
2019-03-13 4:10 ` [PATCH v4 7/7] scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
Add UFS M-PHY driver on MediaTek chipsets.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/Kconfig | 9 ++
drivers/phy/mediatek/Makefile | 1 +
drivers/phy/mediatek/phy-mtk-ufs.c | 239 +++++++++++++++++++++++++++++
3 files changed, 249 insertions(+)
create mode 100644 drivers/phy/mediatek/phy-mtk-ufs.c
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 8857d00b3c65..4a20110a511d 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -21,3 +21,12 @@ config PHY_MTK_XSPHY
Enable this to support the SuperSpeedPlus XS-PHY transceiver for
USB3.1 GEN2 controllers on MediaTek chips. The driver supports
multiple USB2.0, USB3.1 GEN2 ports.
+
+config PHY_MTK_UFS
+ tristate "MediaTek UFS M-PHY driver"
+ depends on ARCH_MEDIATEK && OF
+ select GENERIC_PHY
+ help
+ Support for UFS M-PHY on MediaTek chipsets. Enable this to provide
+ vendor-specific initialization, power on and off flow of specified
+ M-PHYs.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index ee49edc97ee9..14e9aa0b8aa4 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
+obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c
new file mode 100644
index 000000000000..4ff4abdf90e2
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-ufs.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Stanley Chu <stanley.chu@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+/* mphy register and offsets */
+#define MP_GLB_DIG_8C 0x008C
+#define FRC_PLL_ISO_EN BIT(8)
+#define PLL_ISO_EN BIT(9)
+#define FRC_FRC_PWR_ON BIT(10)
+#define PLL_PWR_ON BIT(11)
+
+#define MP_LN_DIG_RX_9C 0xA09C
+#define FSM_DIFZ_FRC BIT(18)
+
+#define MP_LN_DIG_RX_AC 0xA0AC
+#define FRC_RX_SQ_EN BIT(0)
+#define RX_SQ_EN BIT(1)
+
+#define MP_LN_RX_44 0xB044
+#define FRC_CDR_PWR_ON BIT(17)
+#define CDR_PWR_ON BIT(18)
+#define FRC_CDR_ISO_EN BIT(19)
+#define CDR_ISO_EN BIT(20)
+
+#define mphy_readl(phy, ofs) readl((phy)->mmio + (ofs))
+#define mphy_writel(phy, val, ofs) writel((val), (phy)->mmio + (ofs))
+
+struct ufs_mtk_phy {
+ struct device *dev;
+ void __iomem *mmio;
+ struct clk *mp_clk;
+ struct clk *unipro_clk;
+};
+
+static inline void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 ofs)
+{
+ u32 val;
+
+ val = mphy_readl(phy, reg);
+ val |= ofs;
+ mphy_writel(phy, val, reg);
+}
+
+static inline void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 ofs)
+{
+ u32 val;
+
+ val = mphy_readl(phy, reg);
+ val &= ~ofs;
+ mphy_writel(phy, val, reg);
+}
+
+static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy)
+{
+ return (struct ufs_mtk_phy *)phy_get_drvdata(generic_phy);
+}
+
+static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy)
+{
+ struct device *dev = phy->dev;
+
+ phy->unipro_clk = devm_clk_get(dev, "unipro-clk");
+ if (IS_ERR(phy->unipro_clk)) {
+ dev_err(dev, "failed to get unipro-clk");
+ return PTR_ERR(phy->unipro_clk);
+ }
+
+ phy->mp_clk = devm_clk_get(dev, "mp-clk");
+ if (IS_ERR(phy->mp_clk)) {
+ dev_err(dev, "failed to get mp-clk");
+ return PTR_ERR(phy->mp_clk);
+ }
+
+ return 0;
+}
+
+static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy)
+{
+ /* release DA_MP_PLL_PWR_ON */
+ mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
+ mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
+
+ /* release DA_MP_PLL_ISO_EN */
+ mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
+ mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
+
+ /* release DA_MP_CDR_PWR_ON */
+ mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
+ mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
+
+ /* release DA_MP_CDR_ISO_EN */
+ mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
+ mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
+
+ /* release DA_MP_RX0_SQ_EN */
+ mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
+ mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
+
+ /* delay 1us to wait DIFZ stable */
+ udelay(1);
+
+ /* release DIFZ */
+ mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
+}
+
+static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy)
+{
+ /* force DIFZ */
+ mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
+
+ /* force DA_MP_RX0_SQ_EN */
+ mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
+ mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
+
+ /* force DA_MP_CDR_ISO_EN */
+ mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
+ mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
+
+ /* force DA_MP_CDR_PWR_ON */
+ mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
+ mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
+
+ /* force DA_MP_PLL_ISO_EN */
+ mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
+ mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
+
+ /* force DA_MP_PLL_PWR_ON */
+ mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
+ mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
+}
+
+static int ufs_mtk_phy_power_on(struct phy *generic_phy)
+{
+ struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
+ int ret;
+
+ ret = clk_prepare_enable(phy->unipro_clk);
+ if (ret) {
+ dev_err(phy->dev, "unipro_clk enable failed %d\n", ret);
+ goto out;
+ }
+
+ ret = clk_prepare_enable(phy->mp_clk);
+ if (ret) {
+ dev_err(phy->dev, "mp_clk enable failed %d\n", ret);
+ goto out_unprepare_unipro_clk;
+ }
+
+ ufs_mtk_phy_set_active(phy);
+
+ return 0;
+
+out_unprepare_unipro_clk:
+ clk_disable_unprepare(phy->unipro_clk);
+out:
+ return ret;
+}
+
+static int ufs_mtk_phy_power_off(struct phy *generic_phy)
+{
+ struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
+
+ ufs_mtk_phy_set_deep_hibern(phy);
+
+ clk_disable_unprepare(phy->unipro_clk);
+ clk_disable_unprepare(phy->mp_clk);
+
+ return 0;
+}
+
+static const struct phy_ops ufs_mtk_phy_ops = {
+ .power_on = ufs_mtk_phy_power_on,
+ .power_off = ufs_mtk_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int ufs_mtk_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy *generic_phy;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ struct ufs_mtk_phy *phy;
+ int ret;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy->mmio = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy->mmio))
+ return PTR_ERR(phy->mmio);
+
+ phy->dev = dev;
+
+ ret = ufs_mtk_phy_clk_init(phy);
+ if (ret)
+ return ret;
+
+ generic_phy = devm_phy_create(dev, NULL, &ufs_mtk_phy_ops);
+ if (IS_ERR(generic_phy))
+ return PTR_ERR(generic_phy);
+
+ phy_set_drvdata(generic_phy, phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id ufs_mtk_phy_of_match[] = {
+ {.compatible = "mediatek,mt8183-ufsphy"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, ufs_mtk_phy_of_match);
+
+static struct platform_driver ufs_mtk_phy_driver = {
+ .probe = ufs_mtk_phy_probe,
+ .driver = {
+ .of_match_table = ufs_mtk_phy_of_match,
+ .name = "ufs_mtk_phy",
+ },
+};
+module_platform_driver(ufs_mtk_phy_driver);
+
+MODULE_DESCRIPTION("Universal Flash Storage (UFS) MediaTek MPHY");
+MODULE_AUTHOR("Stanley Chu <stanley.chu@medaitek.com>");
+MODULE_LICENSE("GPL v2");
+
--
2.18.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v4 7/7] scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips
2019-03-13 4:10 scsi: ufs-mediatek: Add UFS support for Mediatek SoC chips Stanley Chu
` (6 preceding siblings ...)
2019-03-13 4:10 ` [PATCH v4 6/7] phy: mediatek: Add UFS M-PHY driver Stanley Chu
@ 2019-03-13 4:10 ` Stanley Chu
7 siblings, 0 replies; 9+ messages in thread
From: Stanley Chu @ 2019-03-13 4:10 UTC (permalink / raw)
To: linux-scsi, devicetree, robh+dt, robh, mark.rutland, chunfeng.yun,
kishon, martin.petersen, avri.altman, alim.akhtar, pedrom.sousa
Cc: vivek.gautam, subhashj, liwei213, linux-mediatek, matthias.bgg,
kuohong.wang, peter.wang, chun-hung.wu, Stanley Chu
This patch adds UFS support for MediaTek SoC chips.
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Avri Altman <avri.altman@wdc.com>
---
drivers/scsi/ufs/Kconfig | 14 ++
drivers/scsi/ufs/Makefile | 1 +
drivers/scsi/ufs/ufs-mediatek.c | 368 ++++++++++++++++++++++++++++++++
drivers/scsi/ufs/ufs-mediatek.h | 54 +++++
4 files changed, 437 insertions(+)
create mode 100644 drivers/scsi/ufs/ufs-mediatek.c
create mode 100644 drivers/scsi/ufs/ufs-mediatek.h
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
index 2ddbb26d9c26..58e5a9c8eb5d 100644
--- a/drivers/scsi/ufs/Kconfig
+++ b/drivers/scsi/ufs/Kconfig
@@ -109,6 +109,20 @@ config SCSI_UFS_QCOM
Select this if you have UFS controller on QCOM chipset.
If unsure, say N.
+config SCSI_UFS_MEDIATEK
+ tristate "Mediatek specific hooks to UFS controller platform driver"
+ depends on SCSI_UFSHCD_PLATFORM && ARCH_MEDIATEK
+ select PHY_MTK_UFS
+ help
+ This selects the Mediatek specific additions to UFSHCD platform driver.
+ UFS host on Mediatek needs some vendor specific configuration before
+ accessing the hardware which includes PHY configuration and vendor
+ specific registers.
+
+ Select this if you have UFS controller on Mediatek chipset.
+
+ If unsure, say N.
+
config SCSI_UFS_HISI
tristate "Hisilicon specific hooks to UFS controller platform driver"
depends on (ARCH_HISI || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
index a3bd70c3652c..2a9097939bcb 100644
--- a/drivers/scsi/ufs/Makefile
+++ b/drivers/scsi/ufs/Makefile
@@ -10,3 +10,4 @@ ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o
obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
+obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
new file mode 100644
index 000000000000..88f714cfef59
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-mediatek.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Authors:
+ * Stanley Chu <stanley.chu@mediatek.com>
+ * Peter Wang <peter.wang@mediatek.com>
+ */
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#include "ufshcd.h"
+#include "ufshcd-pltfrm.h"
+#include "unipro.h"
+#include "ufs-mediatek.h"
+
+void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
+{
+ u32 tmp;
+
+ if (enable) {
+ ufshcd_dme_get(hba,
+ UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
+ tmp = tmp |
+ (1 << RX_SYMBOL_CLK_GATE_EN) |
+ (1 << SYS_CLK_GATE_EN) |
+ (1 << TX_CLK_GATE_EN);
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
+
+ ufshcd_dme_get(hba,
+ UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
+ tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
+ } else {
+ ufshcd_dme_get(hba,
+ UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
+ tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
+ (1 << SYS_CLK_GATE_EN) |
+ (1 << TX_CLK_GATE_EN));
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
+
+ ufshcd_dme_get(hba,
+ UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
+ tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
+ ufshcd_dme_set(hba,
+ UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
+ }
+}
+
+int ufs_mtk_bind_mphy(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ struct device *dev = hba->dev;
+ struct device_node *np = dev->of_node;
+ int err = 0;
+
+ host->mphy = devm_of_phy_get_by_index(dev, np, 0);
+
+ if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
+ /*
+ * UFS driver might be probed before the phy driver does.
+ * In that case we would like to return EPROBE_DEFER code.
+ */
+ err = -EPROBE_DEFER;
+ dev_info(dev,
+ "%s: required phy hasn't probed yet. err = %d\n",
+ __func__, err);
+ } else if (IS_ERR(host->mphy)) {
+ err = PTR_ERR(host->mphy);
+ dev_info(dev, "%s: PHY get failed %d\n", __func__, err);
+ }
+
+ if (err)
+ host->mphy = NULL;
+
+ return err;
+}
+
+/**
+ * ufs_mtk_setup_clocks - enables/disable clocks
+ * @hba: host controller instance
+ * @on: If true, enable clocks else disable them.
+ * @status: PRE_CHANGE or POST_CHANGE notify
+ *
+ * Returns 0 on success, non-zero on failure.
+ */
+static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
+ enum ufs_notify_change_status status)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ int ret;
+
+ /*
+ * In case ufs_mtk_init() is not yet done, simply ignore.
+ * This ufs_mtk_setup_clocks() shall be called from
+ * ufs_mtk_init() after init is done.
+ */
+ if (!host)
+ return 0;
+
+ switch (status) {
+ case PRE_CHANGE:
+ if (!on)
+ ret = phy_power_off(host->mphy);
+ break;
+ case POST_CHANGE:
+ if (on)
+ ret = phy_power_on(host->mphy);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * ufs_mtk_init - find other essential mmio bases
+ * @hba: host controller instance
+ *
+ * Binds PHY with controller and powers up PHY enabling clocks
+ * and regulators.
+ *
+ * Returns -EPROBE_DEFER if binding fails, returns negative error
+ * on phy power up failure and returns zero on success.
+ */
+static int ufs_mtk_init(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host;
+ struct device *dev = hba->dev;
+ int err = 0;
+
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+ if (!host) {
+ err = -ENOMEM;
+ dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
+ goto out;
+ }
+
+ host->hba = hba;
+ ufshcd_set_variant(hba, host);
+
+ err = ufs_mtk_bind_mphy(hba);
+ if (err)
+ goto out_variant_clear;
+
+ /*
+ * ufshcd_vops_init() is invoked after
+ * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
+ * phy clock setup is skipped.
+ *
+ * Enable phy clocks specifically here.
+ */
+ ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
+
+ goto out;
+
+out_variant_clear:
+ ufshcd_set_variant(hba, NULL);
+out:
+ return err;
+}
+
+static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *dev_max_params,
+ struct ufs_pa_layer_attr *dev_req_params)
+{
+ struct ufs_dev_params host_cap;
+ int ret;
+
+ host_cap.tx_lanes = UFS_MTK_LIMIT_NUM_LANES_TX;
+ host_cap.rx_lanes = UFS_MTK_LIMIT_NUM_LANES_RX;
+ host_cap.hs_rx_gear = UFS_MTK_LIMIT_HSGEAR_RX;
+ host_cap.hs_tx_gear = UFS_MTK_LIMIT_HSGEAR_TX;
+ host_cap.pwm_rx_gear = UFS_MTK_LIMIT_PWMGEAR_RX;
+ host_cap.pwm_tx_gear = UFS_MTK_LIMIT_PWMGEAR_TX;
+ host_cap.rx_pwr_pwm = UFS_MTK_LIMIT_RX_PWR_PWM;
+ host_cap.tx_pwr_pwm = UFS_MTK_LIMIT_TX_PWR_PWM;
+ host_cap.rx_pwr_hs = UFS_MTK_LIMIT_RX_PWR_HS;
+ host_cap.tx_pwr_hs = UFS_MTK_LIMIT_TX_PWR_HS;
+ host_cap.hs_rate = UFS_MTK_LIMIT_HS_RATE;
+ host_cap.desired_working_mode =
+ UFS_MTK_LIMIT_DESIRED_MODE;
+
+ ret = ufshcd_get_pwr_dev_param(&host_cap,
+ dev_max_params,
+ dev_req_params);
+ if (ret) {
+ pr_info("%s: failed to determine capabilities\n",
+ __func__);
+ }
+
+ return ret;
+}
+
+static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status stage,
+ struct ufs_pa_layer_attr *dev_max_params,
+ struct ufs_pa_layer_attr *dev_req_params)
+{
+ int ret = 0;
+
+ switch (stage) {
+ case PRE_CHANGE:
+ ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
+ dev_req_params);
+ break;
+ case POST_CHANGE:
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int ufs_mtk_pre_link(struct ufs_hba *hba)
+{
+ int ret;
+ u32 tmp;
+
+ /* disable deep stall */
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
+ if (ret)
+ return ret;
+
+ tmp &= ~(1 << 6);
+
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
+
+ return ret;
+}
+
+static int ufs_mtk_post_link(struct ufs_hba *hba)
+{
+ /* disable device LCC */
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
+
+ /* enable unipro clock gating feature */
+ ufs_mtk_cfg_unipro_cg(hba, true);
+
+ return 0;
+}
+
+static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status stage)
+{
+ int ret = 0;
+
+ switch (stage) {
+ case PRE_CHANGE:
+ ret = ufs_mtk_pre_link(hba);
+ break;
+ case POST_CHANGE:
+ ret = ufs_mtk_post_link(hba);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+ if (ufshcd_is_link_hibern8(hba))
+ phy_power_off(host->mphy);
+
+ return 0;
+}
+
+static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+ if (ufshcd_is_link_hibern8(hba))
+ phy_power_on(host->mphy);
+
+ return 0;
+}
+
+/**
+ * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
+ *
+ * The variant operations configure the necessary controller and PHY
+ * handshake during initialization.
+ */
+static struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
+ .name = "mediatek.ufshci",
+ .init = ufs_mtk_init,
+ .setup_clocks = ufs_mtk_setup_clocks,
+ .link_startup_notify = ufs_mtk_link_startup_notify,
+ .pwr_change_notify = ufs_mtk_pwr_change_notify,
+ .suspend = ufs_mtk_suspend,
+ .resume = ufs_mtk_resume,
+};
+
+/**
+ * ufs_mtk_probe - probe routine of the driver
+ * @pdev: pointer to Platform device handle
+ *
+ * Return zero for success and non-zero for failure
+ */
+static int ufs_mtk_probe(struct platform_device *pdev)
+{
+ int err;
+ struct device *dev = &pdev->dev;
+
+ /* perform generic probe */
+ err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
+ if (err)
+ dev_info(dev, "probe failed %d\n", err);
+
+ return err;
+}
+
+/**
+ * ufs_mtk_remove - set driver_data of the device to NULL
+ * @pdev: pointer to platform device handle
+ *
+ * Always return 0
+ */
+static int ufs_mtk_remove(struct platform_device *pdev)
+{
+ struct ufs_hba *hba = platform_get_drvdata(pdev);
+
+ pm_runtime_get_sync(&(pdev)->dev);
+ ufshcd_remove(hba);
+ return 0;
+}
+
+const struct of_device_id ufs_mtk_of_match[] = {
+ { .compatible = "mediatek,mt8183-ufshci"},
+ {},
+};
+
+static const struct dev_pm_ops ufs_mtk_pm_ops = {
+ .suspend = ufshcd_pltfrm_suspend,
+ .resume = ufshcd_pltfrm_resume,
+ .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
+ .runtime_resume = ufshcd_pltfrm_runtime_resume,
+ .runtime_idle = ufshcd_pltfrm_runtime_idle,
+};
+
+static struct platform_driver ufs_mtk_pltform = {
+ .probe = ufs_mtk_probe,
+ .remove = ufs_mtk_remove,
+ .shutdown = ufshcd_pltfrm_shutdown,
+ .driver = {
+ .name = "ufshcd-mtk",
+ .owner = THIS_MODULE,
+ .pm = &ufs_mtk_pm_ops,
+ .of_match_table = ufs_mtk_of_match,
+ },
+};
+
+module_platform_driver(ufs_mtk_pltform);
+
diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h
new file mode 100644
index 000000000000..cc633b627ef0
--- /dev/null
+++ b/drivers/scsi/ufs/ufs-mediatek.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _UFS_MEDIATEK_H
+#define _UFS_MEDIATEK_H
+
+/*
+ * Vendor specific pre-defined parameters
+ */
+#define UFS_MTK_LIMIT_NUM_LANES_RX 1
+#define UFS_MTK_LIMIT_NUM_LANES_TX 1
+#define UFS_MTK_LIMIT_HSGEAR_RX UFS_HS_G3
+#define UFS_MTK_LIMIT_HSGEAR_TX UFS_HS_G3
+#define UFS_MTK_LIMIT_PWMGEAR_RX UFS_PWM_G4
+#define UFS_MTK_LIMIT_PWMGEAR_TX UFS_PWM_G4
+#define UFS_MTK_LIMIT_RX_PWR_PWM SLOW_MODE
+#define UFS_MTK_LIMIT_TX_PWR_PWM SLOW_MODE
+#define UFS_MTK_LIMIT_RX_PWR_HS FAST_MODE
+#define UFS_MTK_LIMIT_TX_PWR_HS FAST_MODE
+#define UFS_MTK_LIMIT_HS_RATE PA_HS_MODE_B
+#define UFS_MTK_LIMIT_DESIRED_MODE UFS_HS_MODE
+
+/*
+ * Other attributes
+ */
+#define VS_DEBUGCLOCKENABLE 0xD0A1
+#define VS_SAVEPOWERCONTROL 0xD0A6
+#define VS_UNIPROPOWERDOWNCONTROL 0xD0A8
+
+/*
+ * VS_DEBUGCLOCKENABLE
+ */
+enum {
+ TX_SYMBOL_CLK_REQ_FORCE = 5,
+};
+
+/*
+ * VS_SAVEPOWERCONTROL
+ */
+enum {
+ RX_SYMBOL_CLK_GATE_EN = 0,
+ SYS_CLK_GATE_EN = 2,
+ TX_CLK_GATE_EN = 3,
+};
+
+struct ufs_mtk_host {
+ struct ufs_hba *hba;
+ struct phy *mphy;
+};
+
+#endif /* !_UFS_MEDIATEK_H */
+
--
2.18.0
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