* [PATCH 1/7] dt-bindings: arm: asr: add ASR8751C bindings
2019-03-23 14:01 [PATCH 0/7] Add dts files for ASR8751C SoC qiaozhou
@ 2019-03-23 14:01 ` qiaozhou
2019-03-31 6:41 ` Rob Herring
2019-03-23 14:01 ` [PATCH 2/7] dt-bindings: bus: add ASR8751C APB/AXI bindings qiaozhou
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: qiaozhou @ 2019-03-23 14:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree, linux-kernel; +Cc: Qiao Zhou
From: Qiao Zhou <qiaozhou@asrmicro.com>
Add new vendor for ASR and add binding document for ASR8751C SoC and initial
board: aquilac-evb
Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
---
Documentation/devicetree/bindings/arm/asr/asr-8751c.txt | 9 +++++++++
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
2 files changed, 10 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/asr/asr-8751c.txt
diff --git a/Documentation/devicetree/bindings/arm/asr/asr-8751c.txt b/Documentation/devicetree/bindings/arm/asr/asr-8751c.txt
new file mode 100644
index 0000000..af7f816
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/asr/asr-8751c.txt
@@ -0,0 +1,9 @@
+ASR 8751C Platforms Device Tree Bindings
+----------------------------------------------------
+ASR 8751C SoC
+Required root node properties:
+ - compatible = ""asr,8751c";
+
+ASR 8751C AquilaC EVB Board
+Required root node properties:
+ - compatible = "asr,aquilac-evb", "asr,8751c";
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 8162b0e..3e10f13 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -43,6 +43,7 @@ arrow Arrow Electronics
artesyn Artesyn Embedded Technologies Inc.
asahi-kasei Asahi Kasei Corp.
aspeed ASPEED Technology Inc.
+asr ASR Microelectronics(Shanghai) Co., Ltd
asus AsusTek Computer Inc.
atlas Atlas Scientific LLC
atmel Atmel Corporation
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 1/7] dt-bindings: arm: asr: add ASR8751C bindings
2019-03-23 14:01 ` [PATCH 1/7] dt-bindings: arm: asr: add ASR8751C bindings qiaozhou
@ 2019-03-31 6:41 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-03-31 6:41 UTC (permalink / raw)
To: qiaozhou; +Cc: Mark Rutland, devicetree, linux-kernel
On Sat, Mar 23, 2019 at 10:01:22PM +0800, qiaozhou wrote:
> From: Qiao Zhou <qiaozhou@asrmicro.com>
>
> Add new vendor for ASR and add binding document for ASR8751C SoC and initial
> board: aquilac-evb
>
> Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
> ---
> Documentation/devicetree/bindings/arm/asr/asr-8751c.txt | 9 +++++++++
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 2 files changed, 10 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/asr/asr-8751c.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/asr/asr-8751c.txt b/Documentation/devicetree/bindings/arm/asr/asr-8751c.txt
> new file mode 100644
> index 0000000..af7f816
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/asr/asr-8751c.txt
> @@ -0,0 +1,9 @@
> +ASR 8751C Platforms Device Tree Bindings
> +----------------------------------------------------
> +ASR 8751C SoC
> +Required root node properties:
> + - compatible = ""asr,8751c";
> +
> +ASR 8751C AquilaC EVB Board
> +Required root node properties:
> + - compatible = "asr,aquilac-evb", "asr,8751c";
Please convert this to DT schema (yaml) format. Most other SoC families
are converted already.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/7] dt-bindings: bus: add ASR8751C APB/AXI bindings
2019-03-23 14:01 [PATCH 0/7] Add dts files for ASR8751C SoC qiaozhou
2019-03-23 14:01 ` [PATCH 1/7] dt-bindings: arm: asr: add ASR8751C bindings qiaozhou
@ 2019-03-23 14:01 ` qiaozhou
2019-03-31 6:41 ` Rob Herring
2019-03-23 14:01 ` [PATCH 3/7] dt-bindings: clocks: add ASR8751C bindings qiaozhou
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: qiaozhou @ 2019-03-23 14:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree, linux-kernel; +Cc: Qiao Zhou
From: Qiao Zhou <qiaozhou@asrmicro.com>
Add binding documentation for ASR8751C AXI/APB bus that are used
to interface with peripherals. AXI/APB bus follow standard AXI/APB
protocols.
Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
---
Documentation/devicetree/bindings/bus/asr,bus.txt | 42 +++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/asr,bus.txt
diff --git a/Documentation/devicetree/bindings/bus/asr,bus.txt b/Documentation/devicetree/bindings/bus/asr,bus.txt
new file mode 100644
index 0000000..cbb1b6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/asr,bus.txt
@@ -0,0 +1,42 @@
+* ASR AXI/APB Simple Bus
+
+This file documents core properties in ASR AXI and APB bus.
+
+The ASR8751C SoC has APB and AXI buses for cores to access its
+controllers, suchas i2c, sdh, rtc, clock, power management registers
+etc. Most ASR SoCs share the common architecture for buses.
+Generally APB and AXI bus have a source clock and power control, and
+clock rate can be changed and power can be shutdown in low power mode.
+
+Required properties for AXI bus:
+- compatible: should be "asr,axi-bus", "simple-bus".
+- #address-cells: could be 1, or 2
+- #size-cells: could be 1, or 2
+- reg: iomem address of AXI bus registers
+- ranges: register ranges
+
+Example:
+ axi@d4200000 { /* AXI */
+ compatible = "asr,axi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0xd4200000 0 0x00200000>;
+ ranges = <0 0 0 0xffffffff>;
+
+ };
+
+Required properties for APB bus:
+- compatible: should be "asr,apb-bus", "simple-bus".
+- #address-cells: could be 1, or 2
+- #size-cells: could be 1, or 2
+- reg: iomem address of APB bus registers
+- ranges: register ranges
+
+Example:
+ apb@d4000000 { /* APB */
+ compatible = "asr,apb-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0xd4000000 0 0x00200000>;
+ ranges = <0 0 0 0xffffffff>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 2/7] dt-bindings: bus: add ASR8751C APB/AXI bindings
2019-03-23 14:01 ` [PATCH 2/7] dt-bindings: bus: add ASR8751C APB/AXI bindings qiaozhou
@ 2019-03-31 6:41 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-03-31 6:41 UTC (permalink / raw)
To: qiaozhou; +Cc: Mark Rutland, devicetree, linux-kernel
On Sat, Mar 23, 2019 at 10:01:23PM +0800, qiaozhou wrote:
> From: Qiao Zhou <qiaozhou@asrmicro.com>
>
> Add binding documentation for ASR8751C AXI/APB bus that are used
> to interface with peripherals. AXI/APB bus follow standard AXI/APB
> protocols.
>
> Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
> ---
> Documentation/devicetree/bindings/bus/asr,bus.txt | 42 +++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/asr,bus.txt
>
> diff --git a/Documentation/devicetree/bindings/bus/asr,bus.txt b/Documentation/devicetree/bindings/bus/asr,bus.txt
> new file mode 100644
> index 0000000..cbb1b6e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/asr,bus.txt
> @@ -0,0 +1,42 @@
> +* ASR AXI/APB Simple Bus
> +
> +This file documents core properties in ASR AXI and APB bus.
> +
> +The ASR8751C SoC has APB and AXI buses for cores to access its
> +controllers, suchas i2c, sdh, rtc, clock, power management registers
s/suchas/such as/
> +etc. Most ASR SoCs share the common architecture for buses.
> +Generally APB and AXI bus have a source clock and power control, and
> +clock rate can be changed and power can be shutdown in low power mode.
Then where are the clocks?
> +
> +Required properties for AXI bus:
> +- compatible: should be "asr,axi-bus", "simple-bus".
> +- #address-cells: could be 1, or 2
> +- #size-cells: could be 1, or 2
> +- reg: iomem address of AXI bus registers
> +- ranges: register ranges
> +
> +Example:
> + axi@d4200000 { /* AXI */
> + compatible = "asr,axi-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0 0xd4200000 0 0x00200000>;
> + ranges = <0 0 0 0xffffffff>;
> +
> + };
> +
> +Required properties for APB bus:
> +- compatible: should be "asr,apb-bus", "simple-bus".
> +- #address-cells: could be 1, or 2
> +- #size-cells: could be 1, or 2
> +- reg: iomem address of APB bus registers
> +- ranges: register ranges
> +
> +Example:
> + apb@d4000000 { /* APB */
> + compatible = "asr,apb-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0 0xd4000000 0 0x00200000>;
> + ranges = <0 0 0 0xffffffff>;
> + };
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/7] dt-bindings: clocks: add ASR8751C bindings
2019-03-23 14:01 [PATCH 0/7] Add dts files for ASR8751C SoC qiaozhou
2019-03-23 14:01 ` [PATCH 1/7] dt-bindings: arm: asr: add ASR8751C bindings qiaozhou
2019-03-23 14:01 ` [PATCH 2/7] dt-bindings: bus: add ASR8751C APB/AXI bindings qiaozhou
@ 2019-03-23 14:01 ` qiaozhou
2019-03-31 6:41 ` Rob Herring
2019-03-23 14:01 ` [PATCH 4/7] dt-bindings: serial: add ASR8751C serial bindings qiaozhou
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: qiaozhou @ 2019-03-23 14:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree, linux-kernel; +Cc: Qiao Zhou
From: Qiao Zhou <qiaozhou@asrmicro.com>
Add binding documentation for ASR8751C clocks, which are general gating
fixed rate and fixed ratio clocks derived from system PLL, external
oscillator. These clocks control registers are distributed on different
sub-controller-unit on SoCs, like APMU, MPMU, CIU etc.
Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
---
.../devicetree/bindings/clock/asr,clock.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/asr,clock.txt
diff --git a/Documentation/devicetree/bindings/clock/asr,clock.txt b/Documentation/devicetree/bindings/clock/asr,clock.txt
new file mode 100644
index 0000000..93082a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/asr,clock.txt
@@ -0,0 +1,31 @@
+* Clock Controller of ASR8751C SoCs
+
+clock subsystem generates and supplies clock to various controllers within the
+ASR8751C SoC.
+
+Required Properties:
+
+- compatible: should be "asr,8751c-clock"
+
+- reg: iomem address and length of the clock subsystem. There are 7 places in
+ SOC has clock control logic: "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu",
+ "ddrc".
+- reg-names: register names of each sub control logic.
+- interrupts : Should be the interrupt number
+- #clock-cells: should be 1.
+
+Example:
+
+ soc_clocks: clocks@d4050000{
+ compatible = "asr,8751c-clock";
+ reg = <0x0 0xd4050000 0x0 0x209c>,
+ <0x0 0xd4282800 0x0 0x400>,
+ <0x0 0xd4015000 0x0 0x1000>,
+ <0x0 0xd4090000 0x0 0x1000>,
+ <0x0 0xd4282c00 0x0 0x400>,
+ <0x0 0xd8440000 0x0 0x98>,
+ <0x0 0xd4200000 0x0 0x4280>;
+ reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc";
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 3/7] dt-bindings: clocks: add ASR8751C bindings
2019-03-23 14:01 ` [PATCH 3/7] dt-bindings: clocks: add ASR8751C bindings qiaozhou
@ 2019-03-31 6:41 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-03-31 6:41 UTC (permalink / raw)
To: qiaozhou; +Cc: Mark Rutland, devicetree, linux-kernel
On Sat, Mar 23, 2019 at 10:01:24PM +0800, qiaozhou wrote:
> From: Qiao Zhou <qiaozhou@asrmicro.com>
>
> Add binding documentation for ASR8751C clocks, which are general gating
> fixed rate and fixed ratio clocks derived from system PLL, external
> oscillator. These clocks control registers are distributed on different
> sub-controller-unit on SoCs, like APMU, MPMU, CIU etc.
>
> Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
> ---
> .../devicetree/bindings/clock/asr,clock.txt | 31 ++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/asr,clock.txt
Patch 5 can be combined with this one. It is part of the binding.
>
> diff --git a/Documentation/devicetree/bindings/clock/asr,clock.txt b/Documentation/devicetree/bindings/clock/asr,clock.txt
> new file mode 100644
> index 0000000..93082a4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/asr,clock.txt
> @@ -0,0 +1,31 @@
> +* Clock Controller of ASR8751C SoCs
> +
> +clock subsystem generates and supplies clock to various controllers within the
> +ASR8751C SoC.
> +
> +Required Properties:
> +
> +- compatible: should be "asr,8751c-clock"
> +
> +- reg: iomem address and length of the clock subsystem. There are 7 places in
> + SOC has clock control logic: "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu",
> + "ddrc".
You should probably have a node for each of these blocks if they are
separate blocks. DT nodes should match h/w blocks.
> +- reg-names: register names of each sub control logic.
> +- interrupts : Should be the interrupt number
However, how do all the blocks have a single interrupt unless it's a
shared interrupt.
> +- #clock-cells: should be 1.
Clock controllers need some input clocks to have any output clocks.
> +
> +Example:
> +
> + soc_clocks: clocks@d4050000{
> + compatible = "asr,8751c-clock";
> + reg = <0x0 0xd4050000 0x0 0x209c>,
> + <0x0 0xd4282800 0x0 0x400>,
> + <0x0 0xd4015000 0x0 0x1000>,
> + <0x0 0xd4090000 0x0 0x1000>,
> + <0x0 0xd4282c00 0x0 0x400>,
> + <0x0 0xd8440000 0x0 0x98>,
> + <0x0 0xd4200000 0x0 0x4280>;
> + reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc";
> + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + };
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/7] dt-bindings: serial: add ASR8751C serial bindings
2019-03-23 14:01 [PATCH 0/7] Add dts files for ASR8751C SoC qiaozhou
` (2 preceding siblings ...)
2019-03-23 14:01 ` [PATCH 3/7] dt-bindings: clocks: add ASR8751C bindings qiaozhou
@ 2019-03-23 14:01 ` qiaozhou
2019-03-31 6:41 ` Rob Herring
2019-03-23 14:01 ` [PATCH 5/7] dt-bindings: Add header file of ASR8751C clock driver qiaozhou
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: qiaozhou @ 2019-03-23 14:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree, linux-kernel; +Cc: Qiao Zhou
From: Qiao Zhou <qiaozhou@asrmicro.com>
Add binding documentation for ASR8751C serial device.
Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
---
.../devicetree/bindings/serial/asr-serial.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/asr-serial.txt
diff --git a/Documentation/devicetree/bindings/serial/asr-serial.txt b/Documentation/devicetree/bindings/serial/asr-serial.txt
new file mode 100644
index 0000000..9e0e191
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/asr-serial.txt
@@ -0,0 +1,23 @@
+* UART Controller of ASR8751C SoCs
+
+Required properties:
+- compatible : should be "asr,uart"
+- reg: iomem address and length of uart registers
+- interrupts : Should be the interrupt number
+- clocks: clock required by uart
+- clock-frequency: frequency of clock source
+- dmas: dma channel used by uart tx or rx
+- dma-names: dma name of uart tx or rx
+
+Example:
+
+ uart0: uart@d4017000 {
+ compatible = "asr,uart";
+ reg = <0xd4017000 0x1000>;
+ interrupts = <0 32 0x4>;
+ clock-frequency = <13000000>;
+ dmas = <&pdma0 AP_UART0_RX 1
+ &pdma0 AP_UART0_TX 1>;
+ dma-names = "rx", "tx";
+ clocks = <&soc_clocks ASR_CLK_UART0>;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 4/7] dt-bindings: serial: add ASR8751C serial bindings
2019-03-23 14:01 ` [PATCH 4/7] dt-bindings: serial: add ASR8751C serial bindings qiaozhou
@ 2019-03-31 6:41 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-03-31 6:41 UTC (permalink / raw)
To: qiaozhou; +Cc: Mark Rutland, devicetree, linux-kernel
On Sat, Mar 23, 2019 at 10:01:25PM +0800, qiaozhou wrote:
> From: Qiao Zhou <qiaozhou@asrmicro.com>
>
> Add binding documentation for ASR8751C serial device.
>
> Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
> ---
> .../devicetree/bindings/serial/asr-serial.txt | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/serial/asr-serial.txt
>
> diff --git a/Documentation/devicetree/bindings/serial/asr-serial.txt b/Documentation/devicetree/bindings/serial/asr-serial.txt
> new file mode 100644
> index 0000000..9e0e191
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/asr-serial.txt
> @@ -0,0 +1,23 @@
> +* UART Controller of ASR8751C SoCs
> +
> +Required properties:
> +- compatible : should be "asr,uart"
Needs an SoC specific compatible.
> +- reg: iomem address and length of uart registers
> +- interrupts : Should be the interrupt number
> +- clocks: clock required by uart
> +- clock-frequency: frequency of clock source
> +- dmas: dma channel used by uart tx or rx
> +- dma-names: dma name of uart tx or rx
> +
> +Example:
> +
> + uart0: uart@d4017000 {
> + compatible = "asr,uart";
> + reg = <0xd4017000 0x1000>;
> + interrupts = <0 32 0x4>;
> + clock-frequency = <13000000>;
> + dmas = <&pdma0 AP_UART0_RX 1
> + &pdma0 AP_UART0_TX 1>;
> + dma-names = "rx", "tx";
> + clocks = <&soc_clocks ASR_CLK_UART0>;
> + };
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 5/7] dt-bindings: Add header file of ASR8751C clock driver
2019-03-23 14:01 [PATCH 0/7] Add dts files for ASR8751C SoC qiaozhou
` (3 preceding siblings ...)
2019-03-23 14:01 ` [PATCH 4/7] dt-bindings: serial: add ASR8751C serial bindings qiaozhou
@ 2019-03-23 14:01 ` qiaozhou
2019-03-23 14:01 ` [PATCH 6/7] dt-bindings: add header file of ASR8751C pinctrl driver qiaozhou
2019-03-23 14:01 ` [PATCH 7/7] arm64: dts: add dts files for asr Aquilac SoC qiaozhou
6 siblings, 0 replies; 14+ messages in thread
From: qiaozhou @ 2019-03-23 14:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree, linux-kernel; +Cc: Qiao Zhou
From: Qiao Zhou <qiaozhou@asrmicro.com>
Add header file used by both ASR8751C clock driver and device tree file.
Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
---
include/dt-bindings/clock/asr8751c-clk.h | 252 +++++++++++++++++++++++++++++++
1 file changed, 252 insertions(+)
create mode 100644 include/dt-bindings/clock/asr8751c-clk.h
diff --git a/include/dt-bindings/clock/asr8751c-clk.h b/include/dt-bindings/clock/asr8751c-clk.h
new file mode 100644
index 0000000..e90fe8d
--- /dev/null
+++ b/include/dt-bindings/clock/asr8751c-clk.h
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * asr clock driver file for asr8751c
+ *
+ * Copyright (c) 2019, ASR Microelectronics(Shanghai) Co., Ltd.
+ * Gang Wu <gangwu@asrmicro.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DTS_ASR8751C_CLOCK_H
+#define __DTS_ASR8751C_CLOCK_H
+
+/* fixed clocks and plls */
+#define ASR_CLK_CLK32 1
+#define ASR_CLK_VCTCXO 2
+#define ASR_CLK_PLL1_VCO 3
+#define ASR_CLK_PLL2_VCO 4
+#define ASR_CLK_PLL3_VCO 5
+#define ASR_CLK_PLL4_VCO 6
+#define ASR_CLK_PLL5_VCO 7
+#define ASR_CLK_PLL6_VCO 8
+#define ASR_CLK_PLL7_VCO 9
+#define ASR_CLK_DPLL1_VCO 10
+#define ASR_CLK_DPLL2_VCO 11
+#define ASR_CLK_VCTCXO_3P25M 12
+#define ASR_CLK_VCTCXO_1M 13
+
+#define ASR_CLK_PLL1_D1_2496_VCO 20
+#define ASR_CLK_PLL1_D2_1248_VCO 21
+#define ASR_CLK_PLL1_D3_832_VCO 22
+#define ASR_CLK_PLL1_D4_624_VCO 23
+#define ASR_CLK_PLL1_D5_499_VCO 24
+#define ASR_CLK_PLL2_D1_VCO 25
+#define ASR_CLK_PLL2_D2_VCO 26
+#define ASR_CLK_PLL2_D3_VCO 27
+#define ASR_CLK_PLL2_D4_VCO 28
+#define ASR_CLK_PLL2_D5_VCO 29
+#define ASR_CLK_PLL3_D1_VCO 30
+#define ASR_CLK_PLL3_D2_VCO 31
+#define ASR_CLK_PLL3_D3_VCO 32
+#define ASR_CLK_PLL3_D4_VCO 33
+#define ASR_CLK_PLL3_D5_VCO 34
+#define ASR_CLK_PLL4_D1_VCO 35
+#define ASR_CLK_PLL4_D2_VCO 36
+#define ASR_CLK_PLL4_D3_VCO 37
+#define ASR_CLK_PLL4_D4_VCO 38
+#define ASR_CLK_PLL4_D5_VCO 39
+#define ASR_CLK_PLL5_D1_VCO 40
+#define ASR_CLK_PLL5_D2_VCO 41
+#define ASR_CLK_PLL5_D3_VCO 42
+#define ASR_CLK_PLL5_D4_VCO 43
+#define ASR_CLK_PLL5_D5_VCO 44
+#define ASR_CLK_PLL6_D1_VCO 45
+#define ASR_CLK_PLL6_D2_VCO 46
+#define ASR_CLK_PLL6_D3_VCO 47
+#define ASR_CLK_PLL6_D4_VCO 48
+#define ASR_CLK_PLL6_D5_VCO 49
+#define ASR_CLK_PLL7_D1_VCO 50
+#define ASR_CLK_PLL7_D2_VCO 51
+#define ASR_CLK_PLL7_D3_VCO 52
+#define ASR_CLK_PLL7_D4_VCO 53
+#define ASR_CLK_PLL7_D5_VCO 54
+
+#define ASR_CLK_DPLL1_D1_VCO 55
+#define ASR_CLK_DPLL1_D2_VCO 56
+#define ASR_CLK_DPLL1_D3_VCO 57
+#define ASR_CLK_DPLL1_D4_VCO 58
+#define ASR_CLK_DPLL2_D1_VCO 59
+#define ASR_CLK_DPLL2_D2_VCO 60
+#define ASR_CLK_DPLL2_D3_VCO 61
+#define ASR_CLK_DPLL2_D4_VCO 62
+
+#define ASR_CLK_PLL1_D1_2496 70
+#define ASR_CLK_PLL1_D2_1248 71
+#define ASR_CLK_PLL1_D3_832 72
+#define ASR_CLK_PLL1_D4_624 73
+#define ASR_CLK_PLL1_D5_499 74
+#define ASR_CLK_PLL2_D1 75
+#define ASR_CLK_PLL2_D2 76
+#define ASR_CLK_PLL2_D3 77
+#define ASR_CLK_PLL2_D4 78
+#define ASR_CLK_PLL2_D5 79
+#define ASR_CLK_PLL3_D1 80
+#define ASR_CLK_PLL3_D2 81
+#define ASR_CLK_PLL3_D3 82
+#define ASR_CLK_PLL3_D4 83
+#define ASR_CLK_PLL3_D5 84
+#define ASR_CLK_PLL4_D1 85
+#define ASR_CLK_PLL4_D2 86
+#define ASR_CLK_PLL4_D3 87
+#define ASR_CLK_PLL4_D4 88
+#define ASR_CLK_PLL4_D5 89
+#define ASR_CLK_PLL5_D1 90
+#define ASR_CLK_PLL5_D2 91
+#define ASR_CLK_PLL5_D3 92
+#define ASR_CLK_PLL5_D4 93
+#define ASR_CLK_PLL5_D5 94
+#define ASR_CLK_PLL6_D1 95
+#define ASR_CLK_PLL6_D2 96
+#define ASR_CLK_PLL6_D3 97
+#define ASR_CLK_PLL6_D4 98
+#define ASR_CLK_PLL6_D5 99
+#define ASR_CLK_PLL7_D1 100
+#define ASR_CLK_PLL7_D2 101
+#define ASR_CLK_PLL7_D3 102
+#define ASR_CLK_PLL7_D4 103
+#define ASR_CLK_PLL7_D5 104
+#define ASR_CLK_DPLL1_D1 105
+#define ASR_CLK_DPLL1_D2 106
+#define ASR_CLK_DPLL1_D3 107
+#define ASR_CLK_DPLL1_D4 108
+#define ASR_CLK_DPLL2_D1 109
+#define ASR_CLK_DPLL2_D2 110
+#define ASR_CLK_DPLL2_D3 111
+#define ASR_CLK_DPLL2_D4 112
+
+#define ASR_CLK_PLL1_D6_416 120
+#define ASR_CLK_PLL1_D8_312 121
+#define ASR_CLK_PLL1_D12_208 122
+#define ASR_CLK_PLL1_D32_78 123
+#define ASR_CLK_PLL1_D24_104 124
+#define ASR_CLK_PLL1_D32_78_2 125
+#define ASR_CLK_PLL1_M3D128_58P5 126
+#define ASR_CLK_PLL1_D48_52 127
+#define ASR_CLK_PLL1_D52_48 128
+#define ASR_CLK_PLL1_D78_32 129
+#define ASR_CLK_PLL1_D96_26 130
+#define ASR_CLK_PLL1_D192_13 131
+#define ASR_CLK_PLL1_D384_6P5 132
+#define ASR_CLK_PLL1_D10_249 133
+
+#define ASR_CLK_PLL1_13_WDT 150
+#define ASR_CLK_PLL1_1248 151
+#define ASR_CLK_PLL1_624 152
+#define ASR_CLK_PLL1_832 153
+#define ASR_CLK_PLL1_312 154
+#define ASR_CLK_PLL1_78_UART 155
+#define ASR_CLK_PLL1_104 156
+#define ASR_CLK_PLL1_78 157
+#define ASR_CLK_PLL1_52 158
+#define ASR_CLK_PLL1_48 159
+#define ASR_CLK_PLL1_58P5 160
+#define ASR_CLK_PLL1_52_2 161
+#define ASR_CLK_PLL1_32 162
+#define ASR_CLK_PLL1_208 163
+#define ASR_CLK_PLL1_26 164
+#define ASR_CLK_PLL1_13 165
+#define ASR_CLK_PLL1_6P5 166
+#define ASR_CLK_PLL1_416 167
+#define ASR_CLK_PLL1_499 168
+#define ASR_CLK_PLL1_249 169
+
+/* ddr/axi etc */
+#define ASR_CLK_DDR 180
+#define ASR_CLK_AXI 181
+#define ASR_CLK_CLST0 182
+#define ASR_CLK_CLST1 183
+#define ASR_CLK_CLST2 184
+#define ASR_CLK_CCI_MEM 185
+#define ASR_CLK_DDR_PERF 186
+
+/* apb periphrals */
+#define ASR_CLK_TWSI0 200
+#define ASR_CLK_TWSI1 201
+#define ASR_CLK_TWSI2 202
+#define ASR_CLK_TWSI3 203
+#define ASR_CLK_TWSI4 204
+#define ASR_CLK_TWSI5 205
+#define ASR_CLK_TWSI6 206
+#define ASR_CLK_TWSI7 207
+#define ASR_CLK_TWSI8 208
+#define ASR_CLK_GPIO 209
+#define ASR_CLK_KPC 210
+#define ASR_CLK_AIB 211
+#define ASR_CLK_RTC 212
+#define ASR_CLK_PWM01P 213
+#define ASR_CLK_PWM0 214
+#define ASR_CLK_PWM1 215
+#define ASR_CLK_PWM23P 226
+#define ASR_CLK_PWM2 217
+#define ASR_CLK_PWM3 218
+#define ASR_CLK_UART0 219
+#define ASR_CLK_UART1 220
+#define ASR_CLK_UART2 221
+#define ASR_CLK_THERMAL 222
+#define ASR_CLK_SWJTAG 223
+#define ASR_CLK_IPC 224
+#define ASR_CLK_SSP0 225
+#define ASR_CLK_SSP2 226
+#define ASR_CLK_TIMER0 227
+#define ASR_CLK_TIMER1 228
+#define ASR_CLK_TIMER2 229
+
+/* axi periphrals */
+#define ASR_CLK_USB 230
+#define ASR_CLK_SDH_AXI 231
+#define ASR_CLK_SDH0 232
+#define ASR_CLK_SDH1 233
+#define ASR_CLK_SDH2 234
+#define ASR_CLK_GPU 235
+#define ASR_CLK_GPUBUS 236
+#define ASR_CLK_VPU 237
+#define ASR_CLK_VPUBUS 238
+#define ASR_CLK_DPU_HWCLK 239
+#define ASR_CLK_DPU_PXCLK 240
+#define ASR_CLK_DPU_PCLK 241
+#define ASR_CLK_DPU_MCLK 242
+#define ASR_CLK_DPU_AXICLK 243
+#define ASR_CLK_DPU_DPHYCLK 244
+#define ASR_CLK_DSI_ESC 245
+#define ASR_CLK_DSI_BIT 246
+#define ASR_CLK_ISP 247
+#define ASR_CLK_DMA 248
+#define ASR_CLK_AES 249
+
+#define ASR_CLK_JPEGFNC 250
+#define ASR_CLK_2KAFBC_FNC 251
+#define ASR_CLK_4KAFBC_FNC 252
+#define ASR_CLK_ISP_MCU 253
+#define ASR_CLK_ISP_BUS 254
+#define ASR_CLK_ISP_FNC 255
+#define ASR_CLK_CCIC_FNC 256
+#define ASR_CLK_SC2_AHB 257
+#define ASR_CLK_CCIC1_PHY 258
+#define ASR_CLK_CCIC2_PHY 259
+#define ASR_CLK_CCIC3_PHY 260
+#define ASR_CLK_CSI_FNC 261
+#define ASR_CLK_CAM_M0 262
+#define ASR_CLK_CAM_M1 263
+#define ASR_CLK_CAM_M2 264
+#define ASR_CLK_XM4_FNC 265
+#define ASR_CLK_AFBC_ENC 266
+#define ASR_CLK_AFBC_DEC 267
+#define ASR_CLK_ISP_BLANK 268
+#define ASR_CLK_AUDIO_FNC 270
+#define ASR_CLK_AUDIOIPC 271
+#define ASR_CLK_RIPC 272
+#define ASR_CLK_DBG 280
+#define ASR_CLK_WDT 281
+#define ASR_CLK_MUX_TIMER0 282
+#define ASR_CLK_MUX_SSP0 283
+#define ASR_CLK_MUX_SSP2 284
+#define ASR_CLK_MUX_UART0 285
+#define ASR_CLK_MUX_UART1 286
+#define ASR_CLK_MUX_UART2 287
+#define ASR_CLK_MUX_AES 288
+
+#define ASR_NR_CLKS 300
+#endif /* __DTS_ASR8751C_CLOCK_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6/7] dt-bindings: add header file of ASR8751C pinctrl driver
2019-03-23 14:01 [PATCH 0/7] Add dts files for ASR8751C SoC qiaozhou
` (4 preceding siblings ...)
2019-03-23 14:01 ` [PATCH 5/7] dt-bindings: Add header file of ASR8751C clock driver qiaozhou
@ 2019-03-23 14:01 ` qiaozhou
2019-03-31 6:41 ` Rob Herring
2019-03-23 14:01 ` [PATCH 7/7] arm64: dts: add dts files for asr Aquilac SoC qiaozhou
6 siblings, 1 reply; 14+ messages in thread
From: qiaozhou @ 2019-03-23 14:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree, linux-kernel; +Cc: Qiao Zhou
From: Qiao Zhou <qiaozhou@asrmicro.com>
Add pinctrl definition and configuration of ASR8751C pins. The
configuration contains pull up/down, driver strength, edge detection,
multiple function etc.
Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
---
include/dt-bindings/pinctrl/asr8751c-pinfunc.h | 341 +++++++++++++++++++++++++
1 file changed, 341 insertions(+)
create mode 100644 include/dt-bindings/pinctrl/asr8751c-pinfunc.h
diff --git a/include/dt-bindings/pinctrl/asr8751c-pinfunc.h b/include/dt-bindings/pinctrl/asr8751c-pinfunc.h
new file mode 100644
index 0000000..b326a6d
--- /dev/null
+++ b/include/dt-bindings/pinctrl/asr8751c-pinfunc.h
@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for ASR Aquila pinctrl bindings.
+ *
+ * Copyright (c) 2019, ASR Microelectronics(Shanghai) Co., Ltd.
+ * All rights reserved.
+ *
+ * Author: Tim Wang <timwang@asrmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __DTS_ASR8751C_PINFUNC_H
+#define __DTS_ASR8751C_PINFUNC_H
+
+/*
+ * drive-strength = <value mask>
+ * SLOW0: < 75MHz
+ * SLOW1: < 150MHz
+ * MEDIUM: < 200MHz
+ * FAST: > 200MHz
+ */
+#define DS_SLOW0 pinctrl-single,drive-strength = <0x0000 0x1800>
+#define DS_SLOW1 pinctrl-single,drive-strength = <0x0800 0x1800>
+#define DS_MEDIUM pinctrl-single,drive-strength = <0x1000 0x1800>
+#define DS_FAST pinctrl-single,drive-strength = <0x1800 0x1800>
+
+/*
+ * Edge detect setting
+ * input-schmitt = <value mask>;
+ * input-schmitt-enable = <value enable disable mask>
+ */
+
+/* no edge detect */
+#define EDGE_NONE pinctrl-single,input-schmitt = <0x00 0x30>; \
+ pinctrl-single,input-schmitt-enable = <0x40 0x00 0x40 0x40>
+/* enable edge fall detect only*/
+#define EDGE_FALL pinctrl-single,input-schmitt = <0x20 0x30>; \
+ pinctrl-single,input-schmitt-enable = <0x00 0x00 0x40 0x40>
+/* enable edge rise detect only */
+#define EDGE_RISE pinctrl-single,input-schmitt = <0x10 0x30>; \
+ pinctrl-single,input-schmitt-enable = <0x00 0x00 0x40 0x40>
+/* enable edge fall/rise detect */
+#define EDGE_BOTH pinctrl-single,input-schmitt = <0x30 0x30>; \
+ pinctrl-single,input-schmitt-enable = <0x00 0x00 0x40 0x40>
+
+/*
+ * bias-pullup = <value enable disable mask>;
+ * bias-pulldown = <value enable disable mask>
+ */
+
+/* PULL_SEL controlled by Alternative Function */
+#define PULL_NONE pinctrl-single,bias-pullup = <0x0000 0xc000 0x0000 0xc000>; \
+ pinctrl-single,bias-pulldown = <0x0000 0xa000 0x0000 0xa000>
+/* PULL_SEL controlled by MFPR, enable PULL_UP, disable PULL_DOWN */
+#define PULL_UP pinctrl-single,bias-pullup = <0xc000 0xc000 0x0000 0xc000>; \
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>
+/* PULL_SEL controlled by MFPR, disable PULL_UP, enable PULL_DOWN */
+#define PULL_DOWN pinctrl-single,bias-pullup = <0x8000 0xc000 0x8000 0xc000>; \
+ pinctrl-single,bias-pulldown = <0xa000 0xa000 0x0000 0xa000>
+/* PULL_SEL controlled by MFPR, enable PULL_UP and PULL_DOWN */
+#define PULL_BOTH pinctrl-single,bias-pullup = <0xc000 0xc000 0x8000 0xc000>; \
+ pinctrl-single,bias-pulldown = <0xa000 0xa000 0x8000 0xa000>
+/* PULL_SEL controlled by MFPR, disable PULL_UP and PULL_DOWN */
+#define PULL_FLOAT pinctrl-single,bias-pullup = <0x8000 0x8000 0x0000 0xc000>; \
+ pinctrl-single,bias-pulldown = <0x8000 0x8000 0x0000 0xa000>
+/* Low Power Mode settings */
+/* no LPM setting, LPM state same as active */
+#define LPM_NONE pinctrl-single,low-power-mode = <0x000 0x388>
+/* LPM, output 0 */
+#define LPM_DRIVE_LOW pinctrl-single,low-power-mode = <0x208 0x388>
+/* LPM, output 1*/
+#define LPM_DRIVE_HIGH pinctrl-single,low-power-mode = <0x308 0x388>
+/* LPM, input state */
+#define LPM_FLOAT pinctrl-single,low-power-mode = <0x288 0x388>
+
+/* Active settings */
+#define MFP_DEFAULT DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_NONE
+#define MFP_PULL_UP DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE
+#define MFP_PULL_DOWN DS_MEDIUM;PULL_DOWN;EDGE_NONE;LPM_NONE
+#define MFP_PULL_FLOAT DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE
+
+/* LPM output */
+#define MFP_LPM_DRIVE_HIGH DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_DRIVE_HIGH
+#define MFP_LPM_DRIVE_LOW DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_DRIVE_LOW
+
+/* LPM input */
+#define MFP_LPM_FLOAT DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT
+#define MFP_LPM_PULL_UP DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_FLOAT
+#define MFP_LPM_PULL_DW DS_MEDIUM;PULL_DOWN;EDGE_NONE;LPM_FLOAT
+
+/*
+ * MFP alternative functions 0-7
+ */
+#define AF0 0x0
+#define AF1 0x1
+#define AF2 0x2
+#define AF3 0x3
+#define AF4 0x4
+#define AF5 0x5
+#define AF6 0x6
+#define AF7 0x7
+
+/*
+ * Pin names and MFPR addresses
+ */
+#define MFPR_OFFSET(x) ((x) << 2)
+#define GPIO_00 MFPR_OFFSET(1)
+#define GPIO_01 MFPR_OFFSET(2)
+#define GPIO_02 MFPR_OFFSET(3)
+#define GPIO_03 MFPR_OFFSET(4)
+#define GPIO_04 MFPR_OFFSET(5)
+#define GPIO_05 MFPR_OFFSET(6)
+#define GPIO_06 MFPR_OFFSET(7)
+#define GPIO_07 MFPR_OFFSET(8)
+#define GPIO_08 MFPR_OFFSET(9)
+#define GPIO_09 MFPR_OFFSET(10)
+#define GPIO_10 MFPR_OFFSET(11)
+#define GPIO_11 MFPR_OFFSET(12)
+#define GPIO_12 MFPR_OFFSET(13)
+#define GPIO_13 MFPR_OFFSET(14)
+#define GPIO_14 MFPR_OFFSET(15)
+#define GPIO_15 MFPR_OFFSET(16)
+#define GPIO_16 MFPR_OFFSET(17)
+#define GPIO_17 MFPR_OFFSET(18)
+#define GPIO_18 MFPR_OFFSET(19)
+#define GPIO_19 MFPR_OFFSET(20)
+#define GPIO_20 MFPR_OFFSET(21)
+#define GPIO_21 MFPR_OFFSET(22)
+#define GPIO_22 MFPR_OFFSET(23)
+#define GPIO_23 MFPR_OFFSET(24)
+#define GPIO_24 MFPR_OFFSET(25)
+#define GPIO_25 MFPR_OFFSET(26)
+#define RXTXEN MFPR_OFFSET(27)
+#define PRI_TXFRAME MFPR_OFFSET(28)
+#define SPI0_EN MFPR_OFFSET(29)
+#define RF_RESET_N MFPR_OFFSET(30)
+#define SEC_SYSCLKEN MFPR_OFFSET(31)
+#define PRI_RXFRAME MFPR_OFFSET(32)
+#define PRI_RBDP0_0 MFPR_OFFSET(33)
+#define PRI_RBDP0_1 MFPR_OFFSET(34)
+#define PRI_RBDP0_2 MFPR_OFFSET(35)
+#define PRI_RBDP0_3 MFPR_OFFSET(36)
+#define PRI_RBDP0_4 MFPR_OFFSET(37)
+#define PRI_RBDP0_5 MFPR_OFFSET(38)
+#define PRI_RBDP0_6 MFPR_OFFSET(39)
+#define PRI_RBDP0_7 MFPR_OFFSET(40)
+#define PRI_RBDP0_8 MFPR_OFFSET(41)
+#define PRI_RBDP0_9 MFPR_OFFSET(42)
+#define PRI_RBDP0_10 MFPR_OFFSET(43)
+#define PRI_MCLK MFPR_OFFSET(98)
+#define PRI_RBDP0_11 MFPR_OFFSET(44)
+#define RXTXDATA MFPR_OFFSET(45)
+#define SYSCLK_OUT MFPR_OFFSET(46)
+#define PRI_FCLK MFPR_OFFSET(47)
+#define PRI_RBDP1_0 MFPR_OFFSET(48)
+#define PRI_RBDP1_1 MFPR_OFFSET(49)
+#define SPI0_CLK MFPR_OFFSET(50)
+#define PRI_RBDP1_2 MFPR_OFFSET(51)
+#define PRI_RBDP1_3 MFPR_OFFSET(52)
+#define PRI_RBDP1_4 MFPR_OFFSET(53)
+#define PRI_RBDP1_5 MFPR_OFFSET(54)
+#define PRI_RBDP1_6 MFPR_OFFSET(55)
+#define PRI_RBDP1_7 MFPR_OFFSET(56)
+#define PRI_RBDP1_8 MFPR_OFFSET(57)
+#define PRI_RBDP1_9 MFPR_OFFSET(58)
+#define SPI0_DIO MFPR_OFFSET(59)
+#define PRI_RBDP1_10 MFPR_OFFSET(60)
+#define PRI_RBDP1_11 MFPR_OFFSET(61)
+#define SPI1_EN MFPR_OFFSET(62)
+#define SEC_RXFRAME MFPR_OFFSET(63)
+#define SEC_RBDP0_0 MFPR_OFFSET(64)
+#define SEC_RBDP0_1 MFPR_OFFSET(65)
+#define SEC_RBDP0_2 MFPR_OFFSET(66)
+#define SEC_RBDP0_3 MFPR_OFFSET(67)
+#define SEC_RBDP0_4 MFPR_OFFSET(68)
+#define SEC_RBDP0_5 MFPR_OFFSET(69)
+#define SEC_RBDP0_6 MFPR_OFFSET(70)
+#define SEC_RBDP0_7 MFPR_OFFSET(71)
+#define SEC_RBDP0_8 MFPR_OFFSET(72)
+#define SEC_RBDP0_9 MFPR_OFFSET(73)
+#define SEC_RBDP0_10 MFPR_OFFSET(74)
+#define SEC_MCLK MFPR_OFFSET(99)
+#define SEC_RBDP0_11 MFPR_OFFSET(75)
+#define SPI1_CLK MFPR_OFFSET(76)
+#define SPI1_DIO MFPR_OFFSET(77)
+#define CP_GPO_0 MFPR_OFFSET(78)
+#define CP_GPO_1 MFPR_OFFSET(79)
+#define CP_GPO_2 MFPR_OFFSET(80)
+#define CP_GPO_3 MFPR_OFFSET(81)
+#define CP_GPO_4 MFPR_OFFSET(82)
+#define CP_GPO_5 MFPR_OFFSET(83)
+#define CP_GPO_6 MFPR_OFFSET(84)
+#define CP_GPO_7 MFPR_OFFSET(85)
+#define CP_GPO_8 MFPR_OFFSET(86)
+#define CP_GPO_9 MFPR_OFFSET(87)
+#define CP_GPO_10 MFPR_OFFSET(88)
+#define CP_GPO_11 MFPR_OFFSET(89)
+#define CP_GPO_12 MFPR_OFFSET(90)
+#define CP_GPO_13 MFPR_OFFSET(91)
+#define CP_GPO_14 MFPR_OFFSET(92)
+#define CP_GPO_15 MFPR_OFFSET(93)
+#define CP_UART_RXD MFPR_OFFSET(94)
+#define CP_UART_TXD MFPR_OFFSET(95)
+#define CP_UART_RTS MFPR_OFFSET(96)
+#define CP_UART_CTS MFPR_OFFSET(97)
+#define USIM2_UCLK MFPR_OFFSET(100)
+#define USIM2_UIO MFPR_OFFSET(101)
+#define USIM2_URSTn MFPR_OFFSET(102)
+#define USIM_UCLK MFPR_OFFSET(103)
+#define USIM_UIO MFPR_OFFSET(104)
+#define USIM_URSTn MFPR_OFFSET(105)
+#define MMC1_DAT3 MFPR_OFFSET(110)
+#define MMC1_DAT2 MFPR_OFFSET(111)
+#define MMC1_DAT1 MFPR_OFFSET(112)
+#define MMC1_DAT0 MFPR_OFFSET(113)
+#define MMC1_CMD MFPR_OFFSET(114)
+#define MMC1_CLK MFPR_OFFSET(115)
+#define PWR_SCL MFPR_OFFSET(118)
+#define PWR_SDA MFPR_OFFSET(119)
+#define VCXO_EN MFPR_OFFSET(120)
+#define VBAT_DROP MFPR_OFFSET(121)
+#define PMIC_INT_N MFPR_OFFSET(122)
+#define PRI_TDI MFPR_OFFSET(123)
+#define PRI_TMS MFPR_OFFSET(124)
+#define PRI_TCK MFPR_OFFSET(125)
+#define PRI_TDO MFPR_OFFSET(126)
+#define SLAVE_RESET_OUT MFPR_OFFSET(127)
+#define VCXO_REQ1 MFPR_OFFSET(128)
+#define VCXO_REQ MFPR_OFFSET(129)
+#define VCXO_OUT MFPR_OFFSET(130)
+#define GPIO_26 MFPR_OFFSET(131)
+#define GPIO_27 MFPR_OFFSET(132)
+#define GPIO_28 MFPR_OFFSET(133)
+#define GPIO_29 MFPR_OFFSET(134)
+#define GPIO_30 MFPR_OFFSET(135)
+#define GPIO_31 MFPR_OFFSET(136)
+#define GPIO_32 MFPR_OFFSET(137)
+#define GPIO_33 MFPR_OFFSET(138)
+#define GPIO_34 MFPR_OFFSET(139)
+#define GPIO_35 MFPR_OFFSET(140)
+#define GPIO_36 MFPR_OFFSET(141)
+#define GPIO_37 MFPR_OFFSET(142)
+#define GPIO_38 MFPR_OFFSET(143)
+#define GPIO_39 MFPR_OFFSET(144)
+#define GPIO_40 MFPR_OFFSET(145)
+#define GPIO_41 MFPR_OFFSET(146)
+#define GPIO_42 MFPR_OFFSET(147)
+#define GPIO_43 MFPR_OFFSET(148)
+#define GPIO_44 MFPR_OFFSET(149)
+#define GPIO_45 MFPR_OFFSET(150)
+#define GPIO_46 MFPR_OFFSET(151)
+#define GPIO_47 MFPR_OFFSET(152)
+#define GPIO_48 MFPR_OFFSET(153)
+#define GPIO_49 MFPR_OFFSET(154)
+#define GPIO_50 MFPR_OFFSET(155)
+#define GPIO_51 MFPR_OFFSET(156)
+#define GPIO_52 MFPR_OFFSET(157)
+#define GPIO_53 MFPR_OFFSET(158)
+#define GPIO_54 MFPR_OFFSET(159)
+#define GPIO_55 MFPR_OFFSET(160)
+#define GPIO_56 MFPR_OFFSET(161)
+#define GPIO_57 MFPR_OFFSET(162)
+#define GPIO_58 MFPR_OFFSET(163)
+#define GPIO_59 MFPR_OFFSET(164)
+#define GPIO_60 MFPR_OFFSET(165)
+#define GPIO_61 MFPR_OFFSET(166)
+#define GPIO_62 MFPR_OFFSET(167)
+#define GPIO_63 MFPR_OFFSET(168)
+#define GPIO_64 MFPR_OFFSET(169)
+#define GPIO_65 MFPR_OFFSET(170)
+#define GPIO_66 MFPR_OFFSET(171)
+#define GPIO_67 MFPR_OFFSET(172)
+#define GPIO_68 MFPR_OFFSET(173)
+#define GPIO_69 MFPR_OFFSET(174)
+#define GPIO_70 MFPR_OFFSET(175)
+#define GPIO_71 MFPR_OFFSET(176)
+#define GPIO_72 MFPR_OFFSET(177)
+#define GPIO_73 MFPR_OFFSET(178)
+#define GPIO_74 MFPR_OFFSET(179)
+#define GPIO_75 MFPR_OFFSET(180)
+#define GPIO_76 MFPR_OFFSET(181)
+#define GPIO_77 MFPR_OFFSET(182)
+#define GPIO_78 MFPR_OFFSET(183)
+#define GPIO_79 MFPR_OFFSET(184)
+#define GPIO_80 MFPR_OFFSET(185)
+#define GPIO_81 MFPR_OFFSET(186)
+#define GPIO_82 MFPR_OFFSET(187)
+#define GPIO_83 MFPR_OFFSET(188)
+#define GPIO_84 MFPR_OFFSET(189)
+#define GPIO_85 MFPR_OFFSET(190)
+#define GPIO_86 MFPR_OFFSET(191)
+#define GPIO_87 MFPR_OFFSET(192)
+#define GPIO_88 MFPR_OFFSET(193)
+#define GPIO_89 MFPR_OFFSET(194)
+#define GPIO_90 MFPR_OFFSET(195)
+#define GPIO_91 MFPR_OFFSET(196)
+#define GPIO_92 MFPR_OFFSET(197)
+#define GPIO_93 MFPR_OFFSET(198)
+#define GPIO_94 MFPR_OFFSET(199)
+#define GPIO_95 MFPR_OFFSET(200)
+#define GPIO_96 MFPR_OFFSET(201)
+#define GPIO_97 MFPR_OFFSET(202)
+#define GPIO_98 MFPR_OFFSET(203)
+#define GPIO_99 MFPR_OFFSET(204)
+#define GPIO_100 MFPR_OFFSET(205)
+#define GPIO_101 MFPR_OFFSET(206)
+#define GPIO_102 MFPR_OFFSET(207)
+#define GPIO_103 MFPR_OFFSET(208)
+#define GPIO_104 MFPR_OFFSET(209)
+#define GPIO_105 MFPR_OFFSET(210)
+#define GPIO_106 MFPR_OFFSET(211)
+#define GPIO_107 MFPR_OFFSET(212)
+#define GPIO_108 MFPR_OFFSET(213)
+#define GPIO_109 MFPR_OFFSET(214)
+#define GPIO_110 MFPR_OFFSET(215)
+#define GPIO_111 MFPR_OFFSET(216)
+#define GPIO_112 MFPR_OFFSET(217)
+#define GPIO_113 MFPR_OFFSET(218)
+#define GPIO_114 MFPR_OFFSET(219)
+#define GPIO_115 MFPR_OFFSET(220)
+#define GPIO_116 MFPR_OFFSET(221)
+#define GPIO_117 MFPR_OFFSET(222)
+#define GPIO_118 MFPR_OFFSET(223)
+#define GPIO_119 MFPR_OFFSET(224)
+#define GPIO_120 MFPR_OFFSET(225)
+#define GPIO_121 MFPR_OFFSET(226)
+#define GPIO_122 MFPR_OFFSET(227)
+#define GPIO_123 MFPR_OFFSET(228)
+#define GPIO_124 MFPR_OFFSET(229)
+#define GPIO_125 MFPR_OFFSET(230)
+#define GPIO_126 MFPR_OFFSET(231)
+#define GPIO_127 MFPR_OFFSET(232)
+#endif /* __DTS_ASR8751C_PINFUNC_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 6/7] dt-bindings: add header file of ASR8751C pinctrl driver
2019-03-23 14:01 ` [PATCH 6/7] dt-bindings: add header file of ASR8751C pinctrl driver qiaozhou
@ 2019-03-31 6:41 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-03-31 6:41 UTC (permalink / raw)
To: qiaozhou; +Cc: Mark Rutland, devicetree, linux-kernel
On Sat, Mar 23, 2019 at 10:01:27PM +0800, qiaozhou wrote:
> From: Qiao Zhou <qiaozhou@asrmicro.com>
>
> Add pinctrl definition and configuration of ASR8751C pins. The
> configuration contains pull up/down, driver strength, edge detection,
> multiple function etc.
>
> Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
> ---
> include/dt-bindings/pinctrl/asr8751c-pinfunc.h | 341 +++++++++++++++++++++++++
> 1 file changed, 341 insertions(+)
> create mode 100644 include/dt-bindings/pinctrl/asr8751c-pinfunc.h
>
> diff --git a/include/dt-bindings/pinctrl/asr8751c-pinfunc.h b/include/dt-bindings/pinctrl/asr8751c-pinfunc.h
> new file mode 100644
> index 0000000..b326a6d
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/asr8751c-pinfunc.h
> @@ -0,0 +1,341 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for ASR Aquila pinctrl bindings.
> + *
> + * Copyright (c) 2019, ASR Microelectronics(Shanghai) Co., Ltd.
> + * All rights reserved.
> + *
> + * Author: Tim Wang <timwang@asrmicro.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
Don't need the GPL boilerplate with the SPDX tag.
> + */
> +
> +#ifndef __DTS_ASR8751C_PINFUNC_H
> +#define __DTS_ASR8751C_PINFUNC_H
> +
> +/*
> + * drive-strength = <value mask>
> + * SLOW0: < 75MHz
> + * SLOW1: < 150MHz
> + * MEDIUM: < 200MHz
> + * FAST: > 200MHz
> + */
> +#define DS_SLOW0 pinctrl-single,drive-strength = <0x0000 0x1800>
> +#define DS_SLOW1 pinctrl-single,drive-strength = <0x0800 0x1800>
> +#define DS_MEDIUM pinctrl-single,drive-strength = <0x1000 0x1800>
> +#define DS_FAST pinctrl-single,drive-strength = <0x1800 0x1800>
Don't do complex definitions. Keep it to simple value defines.
> +
> +/*
> + * Edge detect setting
> + * input-schmitt = <value mask>;
> + * input-schmitt-enable = <value enable disable mask>
> + */
> +
> +/* no edge detect */
> +#define EDGE_NONE pinctrl-single,input-schmitt = <0x00 0x30>; \
> + pinctrl-single,input-schmitt-enable = <0x40 0x00 0x40 0x40>
> +/* enable edge fall detect only*/
> +#define EDGE_FALL pinctrl-single,input-schmitt = <0x20 0x30>; \
> + pinctrl-single,input-schmitt-enable = <0x00 0x00 0x40 0x40>
> +/* enable edge rise detect only */
> +#define EDGE_RISE pinctrl-single,input-schmitt = <0x10 0x30>; \
> + pinctrl-single,input-schmitt-enable = <0x00 0x00 0x40 0x40>
> +/* enable edge fall/rise detect */
> +#define EDGE_BOTH pinctrl-single,input-schmitt = <0x30 0x30>; \
> + pinctrl-single,input-schmitt-enable = <0x00 0x00 0x40 0x40>
> +
> +/*
> + * bias-pullup = <value enable disable mask>;
> + * bias-pulldown = <value enable disable mask>
> + */
> +
> +/* PULL_SEL controlled by Alternative Function */
> +#define PULL_NONE pinctrl-single,bias-pullup = <0x0000 0xc000 0x0000 0xc000>; \
> + pinctrl-single,bias-pulldown = <0x0000 0xa000 0x0000 0xa000>
> +/* PULL_SEL controlled by MFPR, enable PULL_UP, disable PULL_DOWN */
> +#define PULL_UP pinctrl-single,bias-pullup = <0xc000 0xc000 0x0000 0xc000>; \
> + pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>
> +/* PULL_SEL controlled by MFPR, disable PULL_UP, enable PULL_DOWN */
> +#define PULL_DOWN pinctrl-single,bias-pullup = <0x8000 0xc000 0x8000 0xc000>; \
> + pinctrl-single,bias-pulldown = <0xa000 0xa000 0x0000 0xa000>
> +/* PULL_SEL controlled by MFPR, enable PULL_UP and PULL_DOWN */
> +#define PULL_BOTH pinctrl-single,bias-pullup = <0xc000 0xc000 0x8000 0xc000>; \
> + pinctrl-single,bias-pulldown = <0xa000 0xa000 0x8000 0xa000>
> +/* PULL_SEL controlled by MFPR, disable PULL_UP and PULL_DOWN */
> +#define PULL_FLOAT pinctrl-single,bias-pullup = <0x8000 0x8000 0x0000 0xc000>; \
> + pinctrl-single,bias-pulldown = <0x8000 0x8000 0x0000 0xa000>
> +/* Low Power Mode settings */
> +/* no LPM setting, LPM state same as active */
> +#define LPM_NONE pinctrl-single,low-power-mode = <0x000 0x388>
> +/* LPM, output 0 */
> +#define LPM_DRIVE_LOW pinctrl-single,low-power-mode = <0x208 0x388>
> +/* LPM, output 1*/
> +#define LPM_DRIVE_HIGH pinctrl-single,low-power-mode = <0x308 0x388>
> +/* LPM, input state */
> +#define LPM_FLOAT pinctrl-single,low-power-mode = <0x288 0x388>
> +
> +/* Active settings */
> +#define MFP_DEFAULT DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_NONE
> +#define MFP_PULL_UP DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_NONE
> +#define MFP_PULL_DOWN DS_MEDIUM;PULL_DOWN;EDGE_NONE;LPM_NONE
> +#define MFP_PULL_FLOAT DS_MEDIUM;PULL_FLOAT;EDGE_NONE;LPM_NONE
> +
> +/* LPM output */
> +#define MFP_LPM_DRIVE_HIGH DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_DRIVE_HIGH
> +#define MFP_LPM_DRIVE_LOW DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_DRIVE_LOW
> +
> +/* LPM input */
> +#define MFP_LPM_FLOAT DS_MEDIUM;PULL_NONE;EDGE_NONE;LPM_FLOAT
> +#define MFP_LPM_PULL_UP DS_MEDIUM;PULL_UP;EDGE_NONE;LPM_FLOAT
> +#define MFP_LPM_PULL_DW DS_MEDIUM;PULL_DOWN;EDGE_NONE;LPM_FLOAT
> +
> +/*
> + * MFP alternative functions 0-7
> + */
> +#define AF0 0x0
> +#define AF1 0x1
> +#define AF2 0x2
> +#define AF3 0x3
> +#define AF4 0x4
> +#define AF5 0x5
> +#define AF6 0x6
> +#define AF7 0x7
> +
> +/*
> + * Pin names and MFPR addresses
> + */
> +#define MFPR_OFFSET(x) ((x) << 2)
> +#define GPIO_00 MFPR_OFFSET(1)
> +#define GPIO_01 MFPR_OFFSET(2)
> +#define GPIO_02 MFPR_OFFSET(3)
> +#define GPIO_03 MFPR_OFFSET(4)
> +#define GPIO_04 MFPR_OFFSET(5)
> +#define GPIO_05 MFPR_OFFSET(6)
> +#define GPIO_06 MFPR_OFFSET(7)
> +#define GPIO_07 MFPR_OFFSET(8)
> +#define GPIO_08 MFPR_OFFSET(9)
> +#define GPIO_09 MFPR_OFFSET(10)
> +#define GPIO_10 MFPR_OFFSET(11)
> +#define GPIO_11 MFPR_OFFSET(12)
> +#define GPIO_12 MFPR_OFFSET(13)
> +#define GPIO_13 MFPR_OFFSET(14)
> +#define GPIO_14 MFPR_OFFSET(15)
> +#define GPIO_15 MFPR_OFFSET(16)
> +#define GPIO_16 MFPR_OFFSET(17)
> +#define GPIO_17 MFPR_OFFSET(18)
> +#define GPIO_18 MFPR_OFFSET(19)
> +#define GPIO_19 MFPR_OFFSET(20)
> +#define GPIO_20 MFPR_OFFSET(21)
> +#define GPIO_21 MFPR_OFFSET(22)
> +#define GPIO_22 MFPR_OFFSET(23)
> +#define GPIO_23 MFPR_OFFSET(24)
> +#define GPIO_24 MFPR_OFFSET(25)
> +#define GPIO_25 MFPR_OFFSET(26)
> +#define RXTXEN MFPR_OFFSET(27)
> +#define PRI_TXFRAME MFPR_OFFSET(28)
> +#define SPI0_EN MFPR_OFFSET(29)
> +#define RF_RESET_N MFPR_OFFSET(30)
> +#define SEC_SYSCLKEN MFPR_OFFSET(31)
> +#define PRI_RXFRAME MFPR_OFFSET(32)
> +#define PRI_RBDP0_0 MFPR_OFFSET(33)
> +#define PRI_RBDP0_1 MFPR_OFFSET(34)
> +#define PRI_RBDP0_2 MFPR_OFFSET(35)
> +#define PRI_RBDP0_3 MFPR_OFFSET(36)
> +#define PRI_RBDP0_4 MFPR_OFFSET(37)
> +#define PRI_RBDP0_5 MFPR_OFFSET(38)
> +#define PRI_RBDP0_6 MFPR_OFFSET(39)
> +#define PRI_RBDP0_7 MFPR_OFFSET(40)
> +#define PRI_RBDP0_8 MFPR_OFFSET(41)
> +#define PRI_RBDP0_9 MFPR_OFFSET(42)
> +#define PRI_RBDP0_10 MFPR_OFFSET(43)
> +#define PRI_MCLK MFPR_OFFSET(98)
> +#define PRI_RBDP0_11 MFPR_OFFSET(44)
> +#define RXTXDATA MFPR_OFFSET(45)
> +#define SYSCLK_OUT MFPR_OFFSET(46)
> +#define PRI_FCLK MFPR_OFFSET(47)
> +#define PRI_RBDP1_0 MFPR_OFFSET(48)
> +#define PRI_RBDP1_1 MFPR_OFFSET(49)
> +#define SPI0_CLK MFPR_OFFSET(50)
> +#define PRI_RBDP1_2 MFPR_OFFSET(51)
> +#define PRI_RBDP1_3 MFPR_OFFSET(52)
> +#define PRI_RBDP1_4 MFPR_OFFSET(53)
> +#define PRI_RBDP1_5 MFPR_OFFSET(54)
> +#define PRI_RBDP1_6 MFPR_OFFSET(55)
> +#define PRI_RBDP1_7 MFPR_OFFSET(56)
> +#define PRI_RBDP1_8 MFPR_OFFSET(57)
> +#define PRI_RBDP1_9 MFPR_OFFSET(58)
> +#define SPI0_DIO MFPR_OFFSET(59)
> +#define PRI_RBDP1_10 MFPR_OFFSET(60)
> +#define PRI_RBDP1_11 MFPR_OFFSET(61)
> +#define SPI1_EN MFPR_OFFSET(62)
> +#define SEC_RXFRAME MFPR_OFFSET(63)
> +#define SEC_RBDP0_0 MFPR_OFFSET(64)
> +#define SEC_RBDP0_1 MFPR_OFFSET(65)
> +#define SEC_RBDP0_2 MFPR_OFFSET(66)
> +#define SEC_RBDP0_3 MFPR_OFFSET(67)
> +#define SEC_RBDP0_4 MFPR_OFFSET(68)
> +#define SEC_RBDP0_5 MFPR_OFFSET(69)
> +#define SEC_RBDP0_6 MFPR_OFFSET(70)
> +#define SEC_RBDP0_7 MFPR_OFFSET(71)
> +#define SEC_RBDP0_8 MFPR_OFFSET(72)
> +#define SEC_RBDP0_9 MFPR_OFFSET(73)
> +#define SEC_RBDP0_10 MFPR_OFFSET(74)
> +#define SEC_MCLK MFPR_OFFSET(99)
> +#define SEC_RBDP0_11 MFPR_OFFSET(75)
> +#define SPI1_CLK MFPR_OFFSET(76)
> +#define SPI1_DIO MFPR_OFFSET(77)
> +#define CP_GPO_0 MFPR_OFFSET(78)
> +#define CP_GPO_1 MFPR_OFFSET(79)
> +#define CP_GPO_2 MFPR_OFFSET(80)
> +#define CP_GPO_3 MFPR_OFFSET(81)
> +#define CP_GPO_4 MFPR_OFFSET(82)
> +#define CP_GPO_5 MFPR_OFFSET(83)
> +#define CP_GPO_6 MFPR_OFFSET(84)
> +#define CP_GPO_7 MFPR_OFFSET(85)
> +#define CP_GPO_8 MFPR_OFFSET(86)
> +#define CP_GPO_9 MFPR_OFFSET(87)
> +#define CP_GPO_10 MFPR_OFFSET(88)
> +#define CP_GPO_11 MFPR_OFFSET(89)
> +#define CP_GPO_12 MFPR_OFFSET(90)
> +#define CP_GPO_13 MFPR_OFFSET(91)
> +#define CP_GPO_14 MFPR_OFFSET(92)
> +#define CP_GPO_15 MFPR_OFFSET(93)
> +#define CP_UART_RXD MFPR_OFFSET(94)
> +#define CP_UART_TXD MFPR_OFFSET(95)
> +#define CP_UART_RTS MFPR_OFFSET(96)
> +#define CP_UART_CTS MFPR_OFFSET(97)
> +#define USIM2_UCLK MFPR_OFFSET(100)
> +#define USIM2_UIO MFPR_OFFSET(101)
> +#define USIM2_URSTn MFPR_OFFSET(102)
> +#define USIM_UCLK MFPR_OFFSET(103)
> +#define USIM_UIO MFPR_OFFSET(104)
> +#define USIM_URSTn MFPR_OFFSET(105)
> +#define MMC1_DAT3 MFPR_OFFSET(110)
> +#define MMC1_DAT2 MFPR_OFFSET(111)
> +#define MMC1_DAT1 MFPR_OFFSET(112)
> +#define MMC1_DAT0 MFPR_OFFSET(113)
> +#define MMC1_CMD MFPR_OFFSET(114)
> +#define MMC1_CLK MFPR_OFFSET(115)
> +#define PWR_SCL MFPR_OFFSET(118)
> +#define PWR_SDA MFPR_OFFSET(119)
> +#define VCXO_EN MFPR_OFFSET(120)
> +#define VBAT_DROP MFPR_OFFSET(121)
> +#define PMIC_INT_N MFPR_OFFSET(122)
> +#define PRI_TDI MFPR_OFFSET(123)
> +#define PRI_TMS MFPR_OFFSET(124)
> +#define PRI_TCK MFPR_OFFSET(125)
> +#define PRI_TDO MFPR_OFFSET(126)
> +#define SLAVE_RESET_OUT MFPR_OFFSET(127)
> +#define VCXO_REQ1 MFPR_OFFSET(128)
> +#define VCXO_REQ MFPR_OFFSET(129)
> +#define VCXO_OUT MFPR_OFFSET(130)
> +#define GPIO_26 MFPR_OFFSET(131)
> +#define GPIO_27 MFPR_OFFSET(132)
> +#define GPIO_28 MFPR_OFFSET(133)
> +#define GPIO_29 MFPR_OFFSET(134)
> +#define GPIO_30 MFPR_OFFSET(135)
> +#define GPIO_31 MFPR_OFFSET(136)
> +#define GPIO_32 MFPR_OFFSET(137)
> +#define GPIO_33 MFPR_OFFSET(138)
> +#define GPIO_34 MFPR_OFFSET(139)
> +#define GPIO_35 MFPR_OFFSET(140)
> +#define GPIO_36 MFPR_OFFSET(141)
> +#define GPIO_37 MFPR_OFFSET(142)
> +#define GPIO_38 MFPR_OFFSET(143)
> +#define GPIO_39 MFPR_OFFSET(144)
> +#define GPIO_40 MFPR_OFFSET(145)
> +#define GPIO_41 MFPR_OFFSET(146)
> +#define GPIO_42 MFPR_OFFSET(147)
> +#define GPIO_43 MFPR_OFFSET(148)
> +#define GPIO_44 MFPR_OFFSET(149)
> +#define GPIO_45 MFPR_OFFSET(150)
> +#define GPIO_46 MFPR_OFFSET(151)
> +#define GPIO_47 MFPR_OFFSET(152)
> +#define GPIO_48 MFPR_OFFSET(153)
> +#define GPIO_49 MFPR_OFFSET(154)
> +#define GPIO_50 MFPR_OFFSET(155)
> +#define GPIO_51 MFPR_OFFSET(156)
> +#define GPIO_52 MFPR_OFFSET(157)
> +#define GPIO_53 MFPR_OFFSET(158)
> +#define GPIO_54 MFPR_OFFSET(159)
> +#define GPIO_55 MFPR_OFFSET(160)
> +#define GPIO_56 MFPR_OFFSET(161)
> +#define GPIO_57 MFPR_OFFSET(162)
> +#define GPIO_58 MFPR_OFFSET(163)
> +#define GPIO_59 MFPR_OFFSET(164)
> +#define GPIO_60 MFPR_OFFSET(165)
> +#define GPIO_61 MFPR_OFFSET(166)
> +#define GPIO_62 MFPR_OFFSET(167)
> +#define GPIO_63 MFPR_OFFSET(168)
> +#define GPIO_64 MFPR_OFFSET(169)
> +#define GPIO_65 MFPR_OFFSET(170)
> +#define GPIO_66 MFPR_OFFSET(171)
> +#define GPIO_67 MFPR_OFFSET(172)
> +#define GPIO_68 MFPR_OFFSET(173)
> +#define GPIO_69 MFPR_OFFSET(174)
> +#define GPIO_70 MFPR_OFFSET(175)
> +#define GPIO_71 MFPR_OFFSET(176)
> +#define GPIO_72 MFPR_OFFSET(177)
> +#define GPIO_73 MFPR_OFFSET(178)
> +#define GPIO_74 MFPR_OFFSET(179)
> +#define GPIO_75 MFPR_OFFSET(180)
> +#define GPIO_76 MFPR_OFFSET(181)
> +#define GPIO_77 MFPR_OFFSET(182)
> +#define GPIO_78 MFPR_OFFSET(183)
> +#define GPIO_79 MFPR_OFFSET(184)
> +#define GPIO_80 MFPR_OFFSET(185)
> +#define GPIO_81 MFPR_OFFSET(186)
> +#define GPIO_82 MFPR_OFFSET(187)
> +#define GPIO_83 MFPR_OFFSET(188)
> +#define GPIO_84 MFPR_OFFSET(189)
> +#define GPIO_85 MFPR_OFFSET(190)
> +#define GPIO_86 MFPR_OFFSET(191)
> +#define GPIO_87 MFPR_OFFSET(192)
> +#define GPIO_88 MFPR_OFFSET(193)
> +#define GPIO_89 MFPR_OFFSET(194)
> +#define GPIO_90 MFPR_OFFSET(195)
> +#define GPIO_91 MFPR_OFFSET(196)
> +#define GPIO_92 MFPR_OFFSET(197)
> +#define GPIO_93 MFPR_OFFSET(198)
> +#define GPIO_94 MFPR_OFFSET(199)
> +#define GPIO_95 MFPR_OFFSET(200)
> +#define GPIO_96 MFPR_OFFSET(201)
> +#define GPIO_97 MFPR_OFFSET(202)
> +#define GPIO_98 MFPR_OFFSET(203)
> +#define GPIO_99 MFPR_OFFSET(204)
> +#define GPIO_100 MFPR_OFFSET(205)
> +#define GPIO_101 MFPR_OFFSET(206)
> +#define GPIO_102 MFPR_OFFSET(207)
> +#define GPIO_103 MFPR_OFFSET(208)
> +#define GPIO_104 MFPR_OFFSET(209)
> +#define GPIO_105 MFPR_OFFSET(210)
> +#define GPIO_106 MFPR_OFFSET(211)
> +#define GPIO_107 MFPR_OFFSET(212)
> +#define GPIO_108 MFPR_OFFSET(213)
> +#define GPIO_109 MFPR_OFFSET(214)
> +#define GPIO_110 MFPR_OFFSET(215)
> +#define GPIO_111 MFPR_OFFSET(216)
> +#define GPIO_112 MFPR_OFFSET(217)
> +#define GPIO_113 MFPR_OFFSET(218)
> +#define GPIO_114 MFPR_OFFSET(219)
> +#define GPIO_115 MFPR_OFFSET(220)
> +#define GPIO_116 MFPR_OFFSET(221)
> +#define GPIO_117 MFPR_OFFSET(222)
> +#define GPIO_118 MFPR_OFFSET(223)
> +#define GPIO_119 MFPR_OFFSET(224)
> +#define GPIO_120 MFPR_OFFSET(225)
> +#define GPIO_121 MFPR_OFFSET(226)
> +#define GPIO_122 MFPR_OFFSET(227)
> +#define GPIO_123 MFPR_OFFSET(228)
> +#define GPIO_124 MFPR_OFFSET(229)
> +#define GPIO_125 MFPR_OFFSET(230)
> +#define GPIO_126 MFPR_OFFSET(231)
> +#define GPIO_127 MFPR_OFFSET(232)
> +#endif /* __DTS_ASR8751C_PINFUNC_H */
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 7/7] arm64: dts: add dts files for asr Aquilac SoC
2019-03-23 14:01 [PATCH 0/7] Add dts files for ASR8751C SoC qiaozhou
` (5 preceding siblings ...)
2019-03-23 14:01 ` [PATCH 6/7] dt-bindings: add header file of ASR8751C pinctrl driver qiaozhou
@ 2019-03-23 14:01 ` qiaozhou
2019-03-31 6:41 ` Rob Herring
6 siblings, 1 reply; 14+ messages in thread
From: qiaozhou @ 2019-03-23 14:01 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree, linux-kernel; +Cc: Qiao Zhou
From: Qiao Zhou <qiaozhou@asrmicro.com>
Add initial dtsi file to support ASR Aquilac SoC. It has two clusters.
Cluster0 has 4 * Cortex-A53 and Cluster1 has 4 * Cortex-A73.
Also add dts file to support ASR Aquilac SoC development board which is
based on ASR AquilaC SoC.
Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/asr/Makefile | 2 +
arch/arm64/boot/dts/asr/asr8751c-aquilac.dts | 58 ++++
arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi | 400 ++++++++++++++++++++++
arch/arm64/boot/dts/asr/asr8751c.dtsi | 460 ++++++++++++++++++++++++++
5 files changed, 921 insertions(+)
create mode 100644 arch/arm64/boot/dts/asr/Makefile
create mode 100644 arch/arm64/boot/dts/asr/asr8751c-aquilac.dts
create mode 100644 arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/asr/asr8751c.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 5bc7533..38f3db0 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -27,3 +27,4 @@ subdir-y += synaptics
subdir-y += ti
subdir-y += xilinx
subdir-y += zte
+subdir-y += asr
diff --git a/arch/arm64/boot/dts/asr/Makefile b/arch/arm64/boot/dts/asr/Makefile
new file mode 100644
index 0000000..b1f31c8
--- /dev/null
+++ b/arch/arm64/boot/dts/asr/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ASR) += asr8751c-aquilac.dtb
diff --git a/arch/arm64/boot/dts/asr/asr8751c-aquilac.dts b/arch/arm64/boot/dts/asr/asr8751c-aquilac.dts
new file mode 100644
index 0000000..076642f
--- /dev/null
+++ b/arch/arm64/boot/dts/asr/asr8751c-aquilac.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for ASR8751C AquilaC SoC
+ * Copyright (c) 2019, ASR Microelectronics(Shanghai) Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "asr8751c.dtsi"
+#include "asr8751c-pinctrl.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "ASR AquilaC Development Board";
+ compatible = "asr,aquilac-evb", "asr,8751c";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ /*
+ * initrd parameters not set in dts file since the ramdisk.img
+ * size need to check in uboot, and the initrd load address and
+ * size will set in uboot stage.
+ */
+ bootargs = "clk_ignore_unused";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ /* address-cell = 2, size-cell = 2 */
+ device_type = "memory";
+ /* start address: 0x100000000, size = 0xC0000000 */
+ reg = <0x1 0x00000000 0x0 0xC0000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ramoops@10c000000 {
+ compatible = "ramoops";
+ reg = <0x1 0x0c000000 0x0 0x0040000>;
+ record-size = <0x7000>;
+ console-size = <0x30000>;
+ ftrace-size = <0x1000>;
+ pmsg-size = <0x1000>;
+ dump-oops = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi b/arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi
new file mode 100644
index 0000000..047049f
--- /dev/null
+++ b/arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi
@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 ASR Microelectronics(Shanghai) Co., Ltd.
+ * Author: Tim Wang <timwang@asrmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include <dt-bindings/pinctrl/asr8751c-pinfunc.h>
+
+&pmx {
+ evb_mfp_pins_group_0: evb_mfp_pins_group_0 {
+ pinctrl-single,pins = <
+ GPIO_124 AF0
+ >;
+ MFP_PULL_DOWN;
+ };
+
+ /* aquilac evb config group */
+ evb_mfp_pins_group_1: evb_mfp_pins_group_1 {
+ pinctrl-single,pins = <
+ GPIO_07 AF0
+ /* I2C */
+ GPIO_03 AF1 /* I2C5 */
+ GPIO_04 AF1
+ GPIO_45 AF1 /* I2C7 */
+ GPIO_46 AF1
+ GPIO_22 AF1 /* I2C2 */
+ GPIO_23 AF1
+ GPIO_112 AF1 /* I2C6 */
+ GPIO_113 AF1
+ GPIO_63 AF1
+ GPIO_64 AF1
+
+ /* I2S */
+ GPIO_31 AF1
+ GPIO_32 AF1
+ GPIO_33 AF1
+ GPIO_34 AF1
+ GPIO_102 AF1
+ GPIO_103 AF1
+ GPIO_104 AF1
+ GPIO_105 AF1
+ /* SH_SSP */
+ GPIO_82 AF1
+ GPIO_83 AF1
+ GPIO_84 AF1
+ GPIO_85 AF1
+ GPIO_86 AF1
+ GPIO_87 AF1
+ GPIO_88 AF1
+ GPIO_89 AF1
+ /* SH_UART */
+ GPIO_61 AF1
+ GPIO_62 AF1
+ /* SSP */
+ GPIO_41 AF1
+ GPIO_42 AF1
+ GPIO_43 AF1
+ GPIO_44 AF1
+ /* UART */
+ GPIO_24 AF0 /* VSP UART */
+ GPIO_25 AF0
+ GPIO_08 AF0
+ GPIO_92 AF1 /* BT_UART */
+ GPIO_93 AF1
+ GPIO_94 AF1
+ GPIO_95 AF1
+ /* CAMERA */
+ GPIO_09 AF0
+ GPIO_10 AF0
+ GPIO_11 AF0
+ GPIO_12 AF0
+ GPIO_13 AF0
+ GPIO_14 AF0
+ GPIO_15 AF1
+ GPIO_16 AF1
+ GPIO_17 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* TWSI0 GPIO */
+ twsi0_pmx_func0: twsi0_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_18 AF0
+ GPIO_19 AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* AP I2C0 */
+ twsi0_pmx_func1: twsi0_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_18 AF1
+ GPIO_19 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* OVT I2C 0 */
+ twsi0_pmx_func2: twsi0_pmx_func2 {
+ pinctrl-single,pins = <
+ GPIO_18 AF2
+ GPIO_19 AF2
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* TWSI1 GPIO */
+ twsi1_pmx_func0: twsi1_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_20 AF0
+ GPIO_21 AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* AP I2C 1 */
+ twsi1_pmx_func1: twsi1_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_20 AF1
+ GPIO_21 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* OVT I2C 1 */
+ twsi1_pmx_func2: twsi1_pmx_func2 {
+ pinctrl-single,pins = <
+ GPIO_20 AF2
+ GPIO_21 AF2
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* AP I2C 4 */
+ twsi4_pmx_func1: twsi4_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_35 AF1
+ GPIO_36 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ ccic1_pmx_func1: ccic1_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_09 AF0
+ GPIO_12 AF0
+ GPIO_15 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ ccic2_pmx_func1: ccic2_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_10 AF0
+ GPIO_13 AF0
+ GPIO_16 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ ccic3_pmx_func1: ccic3_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_11 AF0
+ GPIO_14 AF0
+ GPIO_17 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* MFP_LPM_PULL_UP */
+ gpio126_pmx_func0: gpio126_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_126 AF0
+ >;
+ MFP_LPM_PULL_UP;
+ };
+
+ /* MFP_DEFAULT */
+ gpio126_pmx_func2: gpio126_pmx_func2 {
+ pinctrl-single,pins = <
+ GPIO_126 AF2
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* MFP_LPM_PULL_UP */
+ gpio51_pmx_func0: gpio51_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_51 AF0
+ >;
+ MFP_LPM_PULL_UP;
+ };
+
+ /* MFP_DEFAULT */
+ gpio51_pmx_func2: gpio51_pmx_func2 {
+ pinctrl-single,pins = <
+ GPIO_51 AF2
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* SD card */
+ sdcard_pmx_func0: sdcard_pmx_func0 {
+ pinctrl-single,pins = <
+ MMC1_DAT3 AF0
+ MMC1_DAT2 AF0
+ MMC1_DAT1 AF0
+ MMC1_DAT0 AF0
+ MMC1_CMD AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* MFP_LPM_DRIVE_LOW */
+ sdcard_clk_pmx_func0: sdcard_clk_pmx_func0 {
+ pinctrl-single,pins = <
+ MMC1_CLK AF0
+ >;
+ MFP_LPM_DRIVE_LOW;
+ };
+
+ /* ds fast, no pull, no LPM */
+ sdcard_pmx_func0_fast: sdcard_pmx_func0_fast {
+ pinctrl-single,pins = <
+ MMC1_DAT3 AF0
+ MMC1_DAT2 AF0
+ MMC1_DAT1 AF0
+ MMC1_DAT0 AF0
+ MMC1_CMD AF0
+ >;
+ DS_FAST;PULL_NONE;EDGE_NONE;LPM_NONE;
+ };
+
+ /* ds fast, LPM_DRIVE_LOW */
+ sdcard_clk_pmx_func0_fast: sdcard_clk_pmx_func0_fast {
+ pinctrl-single,pins = <
+ MMC1_CLK AF0
+ >;
+ DS_FAST;PULL_NONE;EDGE_NONE;LPM_DRIVE_LOW;
+ };
+
+ /* JTAG */
+ sdcard_pmx_func2: sdcard_pmx_func2 {
+ pinctrl-single,pins = <
+ MMC1_DAT3 AF2
+ MMC1_DAT2 AF2
+ MMC1_DAT1 AF2
+ MMC1_DAT0 AF2
+ MMC1_CMD AF2
+ MMC1_CLK AF2
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* SDIO card */
+ sdio_pmx_func1: sdio_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_96 AF1 //MMC2_DAT3
+ GPIO_97 AF1 //MMC2_DAT2
+ GPIO_98 AF1 //MMC2_DAT1
+ GPIO_99 AF1 //MMC2_DAT0
+ GPIO_100 AF1 //MMC2_CMD
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* MFP_LPM_DRIVE_LOW */
+ sdio_clk_pmx_func1: sdio_clk_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_101 AF1 //MMC2_CLK
+ >;
+ MFP_LPM_DRIVE_LOW;
+ };
+
+ /* ds fast, no pull, no LPM */
+ sdio_pmx_func1_fast: sdio_pmx_func1_fast {
+ pinctrl-single,pins = <
+ GPIO_96 AF1 //MMC2_DAT3
+ GPIO_97 AF1 //MMC2_DAT2
+ GPIO_98 AF1 //MMC2_DAT1
+ GPIO_99 AF1 //MMC2_DAT0
+ GPIO_100 AF1 //MMC2_CMD
+ >;
+ DS_FAST;PULL_NONE;EDGE_NONE;LPM_NONE;
+ };
+
+ /* ds fast, LPM_DRIVE_LOW */
+ sdio_clk_pmx_func1_fast: sdio_clk_pmx_func1_fast {
+ pinctrl-single,pins = <
+ GPIO_101 AF1 //MMC2_CLK
+ >;
+ DS_FAST;PULL_NONE;EDGE_NONE;LPM_DRIVE_LOW;
+ };
+
+ /* ssp0 default state */
+ ssp0_pmx_func0: ssp0_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_118 AF1 /* clk */
+ GPIO_120 AF1 /* tx */
+ GPIO_121 AF1 /* rx */
+ >;
+ MFP_PULL_DOWN;
+ };
+
+ ssp0_pmx_func1: ssp0_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_119 AF1 /* cs */
+ >;
+ MFP_PULL_UP;
+ };
+
+ /* uart2 */
+ uart2_pmx_func1: uart2_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_120 AF2 /* tx */
+ GPIO_121 AF2 /* rx */
+ >;
+ MFP_DEFAULT;
+ };
+
+ uart2_pmx_func2: uart2_pmx_func2 {
+ pinctrl-single,pins = <
+ GPIO_118 AF2 /* CTS */
+ GPIO_119 AF2 /* RTS */
+ >;
+ MFP_PULL_DOWN;
+ };
+
+ fp_pmx_func1: fp_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_76 AF0
+ GPIO_81 AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+ /* AP I2C 8 */
+ twsi8_pmx_func1: twsi8_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_47 AF1
+ GPIO_48 AF1
+ >;
+ MFP_DEFAULT;
+ };
+
+ nfc_pmx_func0: nfc_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_124 AF0
+ GPIO_123 AF0
+ GPIO_115 AF0
+ VCXO_REQ1 AF1
+ >;
+ MFP_LPM_FLOAT;
+ };
+
+ nfc_pmx_func0_n3_1: nfc_pmx_func0_n3_1 {
+ pinctrl-single,pins = <
+ GPIO_116 AF0
+ GPIO_115 AF0
+ GPIO_60 AF0
+ >;
+ MFP_DEFAULT;
+ };
+
+ nfc_pmx_func0_n3_2: nfc_pmx_func0_n3_2 {
+ pinctrl-single,pins = <
+ GPIO_107 AF0
+ >;
+ MFP_PULL_DOWN;
+ };
+
+ goodix_ts_pmx_func0: goodix_ts_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_05 AF0
+ GPIO_06 AF0
+ >;
+ MFP_PULL_DOWN;
+ };
+
+
+ /* Not used pin, pull down and set input in lpm */
+ evb_sensor_pmx_func0: evb_sensor_pmx_func0 {
+ pinctrl-single,pins = <
+ GPIO_78 AF0
+ >;
+ MFP_PULL_DOWN;
+ };
+
+ /* EVB reset pin for mag sensor, GPIO */
+ evb_sensor_pmx_func1: evb_sensor_pmx_func1 {
+ pinctrl-single,pins = <
+ GPIO_80 AF0
+ >;
+ MFP_PULL_UP;
+ };
+};
diff --git a/arch/arm64/boot/dts/asr/asr8751c.dtsi b/arch/arm64/boot/dts/asr/asr8751c.dtsi
new file mode 100644
index 0000000..c7222eb
--- /dev/null
+++ b/arch/arm64/boot/dts/asr/asr8751c.dtsi
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dtsi file for ASR8751C
+ * Copyright (c) 2019, ASR Microelectronics(Shanghai) Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include <dt-bindings/clock/asr8751c-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_C1: cpu-c1 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0000002>;
+ entry-latency-us = <20>;
+ exit-latency-us = <20>;
+ min-residency-us = <100>;
+ };
+
+ CPU_C2: cpu-c2 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010005>;
+ entry-latency-us = <40>;
+ exit-latency-us = <40>;
+ min-residency-us = <200>;
+ };
+
+ CLUSTER_MP2: cluster-mp2 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010055>;
+ entry-latency-us = <80>;
+ exit-latency-us = <80>;
+ min-residency-us = <400>;
+ wakeup-latency-us = <40>;
+ };
+
+ CHIP_D1P: chip-d1p {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x2010355>;
+ entry-latency-us = <200>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ wakeup-latency-us = <80>;
+ };
+
+ CHIP_D1: chip-d1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x2010455>;
+ entry-latency-us = <300>;
+ exit-latency-us = <300>;
+ min-residency-us = <1200>;
+ wakeup-latency-us = <160>;
+ };
+
+ CHIP_D2: chip-d2 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x2010555>;
+ entry-latency-us = <400>;
+ exit-latency-us = <400>;
+ min-residency-us = <1500>;
+ wakeup-latency-us = <200>;
+ };
+ };
+
+ clst0_core_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp832000000 {
+ opp-hz = /bits/ 64 <832000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <200000>;
+ };
+ opp1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ opp1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ opp1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ opp1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ clst1_core_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ opp1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ opp1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ opp1900000000 {
+ opp-hz = /bits/ 64 <1900000000>;
+ opp-microvolt = <1500000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cpu-map {
+ cluster0: cluster0 {
+ #cooling-cells = <2>; /* min followed by max */
+ dynamic-pwr-coeff = <89>;
+ static-pwr-base-coeff = <1335>;
+ static-pwr-temp-coeff =
+ <2225 27650 (-286) 10>;
+ enable_ipa_vmin_control;
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1: cluster1 {
+ #cooling-cells = <2>;
+ dynamic-pwr-coeff = <115>;
+ static-pwr-base-coeff = <2157>;
+ static-pwr-temp-coeff =
+ <52330 32960 (-603) 13>;
+ enable_ipa_vmin_control;
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
+ clocks = <&soc_clocks ASR_CLK_CLST0>;
+ operating-points-v2 = <&clst0_core_opp_table>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
+ clocks = <&soc_clocks ASR_CLK_CLST0>;
+ operating-points-v2 = <&clst0_core_opp_table>;
+ };
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x2>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
+ clocks = <&soc_clocks ASR_CLK_CLST0>;
+ operating-points-v2 = <&clst0_core_opp_table>;
+ };
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x3>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
+ clocks = <&soc_clocks ASR_CLK_CLST0>;
+ operating-points-v2 = <&clst0_core_opp_table>;
+ };
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
+ clocks = <&soc_clocks ASR_CLK_CLST1>;
+ operating-points-v2 = <&clst1_core_opp_table>;
+ };
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
+ clocks = <&soc_clocks ASR_CLK_CLST1>;
+ operating-points-v2 = <&clst1_core_opp_table>;
+ };
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x102>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
+ clocks = <&soc_clocks ASR_CLK_CLST1>;
+ operating-points-v2 = <&clst1_core_opp_table>;
+ };
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0 0x103>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
+ sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
+ clocks = <&soc_clocks ASR_CLK_CLST1>;
+ operating-points-v2 = <&clst1_core_opp_table>;
+ };
+
+ };
+
+ energy-costs {
+ /* cpu 0 data is magic data without any evidence */
+ CPU_COST_0: core-cost0 {
+ busy-cost-data = <
+ 195 35 /* 624mhz */
+ 260 48 /* 832mhz */
+ 312 64 /* 1000mhz */
+ 390 95 /* 1248mhz */
+ 438 118 /* 1400mhz */
+ 501 149 /* 1600mhz */
+ >;
+ idle-cost-data = <
+ 6
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ >;
+ };
+ CPU_COST_1: core-cost1 {
+ busy-cost-data = <
+ 538 195 /* 1000mhz */
+ 672 292 /* 1248mhz */
+ 862 441 /* 1600mhz */
+ 1024 640 /* 1900mhz */
+
+ >;
+ idle-cost-data = <
+ 8
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ >;
+ };
+ CLUSTER_COST_0: cluster-cost0 {
+ busy-cost-data = <
+ 195 7 /* 624mhz */
+ 260 10 /* 832mhz */
+ 312 13 /* 1000mhz */
+ 390 22 /* 1248mhz */
+ 438 29 /* 1400mhz */
+ 501 39 /* 1600mhz */
+ >;
+ idle-cost-data = <
+ 40
+ 50
+ 0
+ 0
+ 0
+ 0
+ 0
+ >;
+ };
+ CLUSTER_COST_1: cluster-cost1 {
+ busy-cost-data = <
+ 538 20 /* 1000mhz */
+ 672 33 /* 1248mhz */
+ 862 54 /* 1600mhz */
+ 1024 86 /* 1900mhz */
+ >;
+ idle-cost-data = <
+ 50
+ 60
+ 0
+ 0
+ 0
+ 0
+ 0
+ >;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
+ };
+
+ gic: interrupt-controller@d8000000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0 0xd8000000 0x0 0x200000>,
+ <0x0 0xd8100000 0x0 0x200000>;
+ interrupts = <1 9 0x8>;
+ };
+
+ generic-timer {
+ compatible = "arm,armv8-timer";
+ /* PPI secure/nonsecure IRQ, active low level-sensitive */
+ interrupts = <1 13 0x8>,
+ <1 14 0x8>,
+ <1 11 0x8>,
+ <1 10 0x8>;
+ clock-frequency = <26000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ axi@d4200000 { /* AXI */
+ compatible = "asr,axi-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0xd4200000 0 0x00200000>;
+ ranges = <0 0 0 0xffffffff>;
+
+ }; /* AXI */
+
+ apb@d4000000 { /* APB */
+ compatible = "asr,apb-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0xd4000000 0 0x00200000>;
+ ranges = <0 0 0 0xffffffff>;
+
+ uart0: uart@d4017000 {
+ compatible = "asr,uart";
+ reg = <0xd4017000 0x1000>;
+ interrupts = <0 32 0x4>;
+ clock-frequency = <13000000>;
+ clocks = <&soc_clocks ASR_CLK_UART0>;
+ };
+
+ uart1: uart@d4018000 {
+ compatible = "asr,uart";
+ reg = <0xd4018000 0x1000>;
+ interrupts = <0 33 0x4>;
+ clock-frequency = <13000000>;
+ clocks = <&soc_clocks ASR_CLK_UART1>;
+ };
+
+ uart2: uart@d4017800 {
+ compatible = "asr,uart";
+ reg = <0xd4017800 0x1000>;
+ interrupts = <0 34 0x4>;
+ clock-frequency = <13000000>;
+ clocks = <&soc_clocks ASR_CLK_UART2>;
+ };
+
+ pmx: pinmux@d401e000 {
+ compatible = "pinconf-single";
+ reg = <0xd401e000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #gpio-range-cells = <3>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+ }; /* APB */
+ }; /* soc */
+
+ soc_clocks: clocks@d4050000{
+ compatible = "asr,8751c-clock";
+ reg = <0x0 0xd4050000 0x0 0x209c>,
+ <0x0 0xd4282800 0x0 0x400>,
+ <0x0 0xd4015000 0x0 0x1000>,
+ <0x0 0xd4090000 0x0 0x1000>,
+ <0x0 0xd4282c00 0x0 0x400>,
+ <0x0 0xd8440000 0x0 0x98>,
+ <0x0 0xd4200000 0x0 0x4280>;
+ reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc";
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 7/7] arm64: dts: add dts files for asr Aquilac SoC
2019-03-23 14:01 ` [PATCH 7/7] arm64: dts: add dts files for asr Aquilac SoC qiaozhou
@ 2019-03-31 6:41 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-03-31 6:41 UTC (permalink / raw)
To: qiaozhou; +Cc: Mark Rutland, devicetree, linux-kernel
On Sat, Mar 23, 2019 at 10:01:28PM +0800, qiaozhou wrote:
> From: Qiao Zhou <qiaozhou@asrmicro.com>
>
> Add initial dtsi file to support ASR Aquilac SoC. It has two clusters.
> Cluster0 has 4 * Cortex-A53 and Cluster1 has 4 * Cortex-A73.
>
> Also add dts file to support ASR Aquilac SoC development board which is
> based on ASR AquilaC SoC.
>
> Signed-off-by: qiaozhou <qiaozhou@asrmicro.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/asr/Makefile | 2 +
> arch/arm64/boot/dts/asr/asr8751c-aquilac.dts | 58 ++++
> arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi | 400 ++++++++++++++++++++++
> arch/arm64/boot/dts/asr/asr8751c.dtsi | 460 ++++++++++++++++++++++++++
> 5 files changed, 921 insertions(+)
> create mode 100644 arch/arm64/boot/dts/asr/Makefile
> create mode 100644 arch/arm64/boot/dts/asr/asr8751c-aquilac.dts
> create mode 100644 arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/asr/asr8751c.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 5bc7533..38f3db0 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -27,3 +27,4 @@ subdir-y += synaptics
> subdir-y += ti
> subdir-y += xilinx
> subdir-y += zte
> +subdir-y += asr
> diff --git a/arch/arm64/boot/dts/asr/Makefile b/arch/arm64/boot/dts/asr/Makefile
> new file mode 100644
> index 0000000..b1f31c8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/asr/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_ASR) += asr8751c-aquilac.dtb
> diff --git a/arch/arm64/boot/dts/asr/asr8751c-aquilac.dts b/arch/arm64/boot/dts/asr/asr8751c-aquilac.dts
> new file mode 100644
> index 0000000..076642f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/asr/asr8751c-aquilac.dts
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for ASR8751C AquilaC SoC
> + * Copyright (c) 2019, ASR Microelectronics(Shanghai) Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
Drop the boilerplate.
> + */
> +
> +/dts-v1/;
> +#include "asr8751c.dtsi"
> +#include "asr8751c-pinctrl.dtsi"
> +#include <dt-bindings/input/linux-event-codes.h>
> +
> +/ {
> + model = "ASR AquilaC Development Board";
> + compatible = "asr,aquilac-evb", "asr,8751c";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + };
> +
> + chosen {
> + /*
> + * initrd parameters not set in dts file since the ramdisk.img
> + * size need to check in uboot, and the initrd load address and
> + * size will set in uboot stage.
> + */
> + bootargs = "clk_ignore_unused";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
unit address doesn't match.
> + /* address-cell = 2, size-cell = 2 */
> + device_type = "memory";
> + /* start address: 0x100000000, size = 0xC0000000 */
> + reg = <0x1 0x00000000 0x0 0xC0000000>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ramoops@10c000000 {
> + compatible = "ramoops";
> + reg = <0x1 0x0c000000 0x0 0x0040000>;
> + record-size = <0x7000>;
> + console-size = <0x30000>;
> + ftrace-size = <0x1000>;
> + pmsg-size = <0x1000>;
> + dump-oops = <0>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi b/arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi
> new file mode 100644
> index 0000000..047049f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/asr/asr8751c-pinctrl.dtsi
> @@ -0,0 +1,400 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 ASR Microelectronics(Shanghai) Co., Ltd.
> + * Author: Tim Wang <timwang@asrmicro.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
Drop the boilerplate.
> + */
> +#include <dt-bindings/pinctrl/asr8751c-pinfunc.h>
> +
> +&pmx {
> + evb_mfp_pins_group_0: evb_mfp_pins_group_0 {
> + pinctrl-single,pins = <
> + GPIO_124 AF0
> + >;
> + MFP_PULL_DOWN;
> + };
> +
> + /* aquilac evb config group */
> + evb_mfp_pins_group_1: evb_mfp_pins_group_1 {
> + pinctrl-single,pins = <
> + GPIO_07 AF0
> + /* I2C */
> + GPIO_03 AF1 /* I2C5 */
> + GPIO_04 AF1
> + GPIO_45 AF1 /* I2C7 */
> + GPIO_46 AF1
> + GPIO_22 AF1 /* I2C2 */
> + GPIO_23 AF1
> + GPIO_112 AF1 /* I2C6 */
> + GPIO_113 AF1
> + GPIO_63 AF1
> + GPIO_64 AF1
> +
> + /* I2S */
> + GPIO_31 AF1
> + GPIO_32 AF1
> + GPIO_33 AF1
> + GPIO_34 AF1
> + GPIO_102 AF1
> + GPIO_103 AF1
> + GPIO_104 AF1
> + GPIO_105 AF1
> + /* SH_SSP */
> + GPIO_82 AF1
> + GPIO_83 AF1
> + GPIO_84 AF1
> + GPIO_85 AF1
> + GPIO_86 AF1
> + GPIO_87 AF1
> + GPIO_88 AF1
> + GPIO_89 AF1
> + /* SH_UART */
> + GPIO_61 AF1
> + GPIO_62 AF1
> + /* SSP */
> + GPIO_41 AF1
> + GPIO_42 AF1
> + GPIO_43 AF1
> + GPIO_44 AF1
> + /* UART */
> + GPIO_24 AF0 /* VSP UART */
> + GPIO_25 AF0
> + GPIO_08 AF0
> + GPIO_92 AF1 /* BT_UART */
> + GPIO_93 AF1
> + GPIO_94 AF1
> + GPIO_95 AF1
> + /* CAMERA */
> + GPIO_09 AF0
> + GPIO_10 AF0
> + GPIO_11 AF0
> + GPIO_12 AF0
> + GPIO_13 AF0
> + GPIO_14 AF0
> + GPIO_15 AF1
> + GPIO_16 AF1
> + GPIO_17 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* TWSI0 GPIO */
> + twsi0_pmx_func0: twsi0_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_18 AF0
> + GPIO_19 AF0
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* AP I2C0 */
> + twsi0_pmx_func1: twsi0_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_18 AF1
> + GPIO_19 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* OVT I2C 0 */
> + twsi0_pmx_func2: twsi0_pmx_func2 {
> + pinctrl-single,pins = <
> + GPIO_18 AF2
> + GPIO_19 AF2
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* TWSI1 GPIO */
> + twsi1_pmx_func0: twsi1_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_20 AF0
> + GPIO_21 AF0
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* AP I2C 1 */
> + twsi1_pmx_func1: twsi1_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_20 AF1
> + GPIO_21 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* OVT I2C 1 */
> + twsi1_pmx_func2: twsi1_pmx_func2 {
> + pinctrl-single,pins = <
> + GPIO_20 AF2
> + GPIO_21 AF2
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* AP I2C 4 */
> + twsi4_pmx_func1: twsi4_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_35 AF1
> + GPIO_36 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + ccic1_pmx_func1: ccic1_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_09 AF0
> + GPIO_12 AF0
> + GPIO_15 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + ccic2_pmx_func1: ccic2_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_10 AF0
> + GPIO_13 AF0
> + GPIO_16 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + ccic3_pmx_func1: ccic3_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_11 AF0
> + GPIO_14 AF0
> + GPIO_17 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* MFP_LPM_PULL_UP */
> + gpio126_pmx_func0: gpio126_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_126 AF0
> + >;
> + MFP_LPM_PULL_UP;
> + };
> +
> + /* MFP_DEFAULT */
> + gpio126_pmx_func2: gpio126_pmx_func2 {
> + pinctrl-single,pins = <
> + GPIO_126 AF2
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* MFP_LPM_PULL_UP */
> + gpio51_pmx_func0: gpio51_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_51 AF0
> + >;
> + MFP_LPM_PULL_UP;
> + };
> +
> + /* MFP_DEFAULT */
> + gpio51_pmx_func2: gpio51_pmx_func2 {
> + pinctrl-single,pins = <
> + GPIO_51 AF2
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* SD card */
> + sdcard_pmx_func0: sdcard_pmx_func0 {
> + pinctrl-single,pins = <
> + MMC1_DAT3 AF0
> + MMC1_DAT2 AF0
> + MMC1_DAT1 AF0
> + MMC1_DAT0 AF0
> + MMC1_CMD AF0
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* MFP_LPM_DRIVE_LOW */
> + sdcard_clk_pmx_func0: sdcard_clk_pmx_func0 {
> + pinctrl-single,pins = <
> + MMC1_CLK AF0
> + >;
> + MFP_LPM_DRIVE_LOW;
> + };
> +
> + /* ds fast, no pull, no LPM */
> + sdcard_pmx_func0_fast: sdcard_pmx_func0_fast {
> + pinctrl-single,pins = <
> + MMC1_DAT3 AF0
> + MMC1_DAT2 AF0
> + MMC1_DAT1 AF0
> + MMC1_DAT0 AF0
> + MMC1_CMD AF0
> + >;
> + DS_FAST;PULL_NONE;EDGE_NONE;LPM_NONE;
> + };
> +
> + /* ds fast, LPM_DRIVE_LOW */
> + sdcard_clk_pmx_func0_fast: sdcard_clk_pmx_func0_fast {
> + pinctrl-single,pins = <
> + MMC1_CLK AF0
> + >;
> + DS_FAST;PULL_NONE;EDGE_NONE;LPM_DRIVE_LOW;
> + };
> +
> + /* JTAG */
> + sdcard_pmx_func2: sdcard_pmx_func2 {
> + pinctrl-single,pins = <
> + MMC1_DAT3 AF2
> + MMC1_DAT2 AF2
> + MMC1_DAT1 AF2
> + MMC1_DAT0 AF2
> + MMC1_CMD AF2
> + MMC1_CLK AF2
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* SDIO card */
> + sdio_pmx_func1: sdio_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_96 AF1 //MMC2_DAT3
> + GPIO_97 AF1 //MMC2_DAT2
> + GPIO_98 AF1 //MMC2_DAT1
> + GPIO_99 AF1 //MMC2_DAT0
> + GPIO_100 AF1 //MMC2_CMD
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* MFP_LPM_DRIVE_LOW */
> + sdio_clk_pmx_func1: sdio_clk_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_101 AF1 //MMC2_CLK
> + >;
> + MFP_LPM_DRIVE_LOW;
> + };
> +
> + /* ds fast, no pull, no LPM */
> + sdio_pmx_func1_fast: sdio_pmx_func1_fast {
> + pinctrl-single,pins = <
> + GPIO_96 AF1 //MMC2_DAT3
> + GPIO_97 AF1 //MMC2_DAT2
> + GPIO_98 AF1 //MMC2_DAT1
> + GPIO_99 AF1 //MMC2_DAT0
> + GPIO_100 AF1 //MMC2_CMD
> + >;
> + DS_FAST;PULL_NONE;EDGE_NONE;LPM_NONE;
> + };
> +
> + /* ds fast, LPM_DRIVE_LOW */
> + sdio_clk_pmx_func1_fast: sdio_clk_pmx_func1_fast {
> + pinctrl-single,pins = <
> + GPIO_101 AF1 //MMC2_CLK
> + >;
> + DS_FAST;PULL_NONE;EDGE_NONE;LPM_DRIVE_LOW;
> + };
> +
> + /* ssp0 default state */
> + ssp0_pmx_func0: ssp0_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_118 AF1 /* clk */
> + GPIO_120 AF1 /* tx */
> + GPIO_121 AF1 /* rx */
> + >;
> + MFP_PULL_DOWN;
> + };
> +
> + ssp0_pmx_func1: ssp0_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_119 AF1 /* cs */
> + >;
> + MFP_PULL_UP;
> + };
> +
> + /* uart2 */
> + uart2_pmx_func1: uart2_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_120 AF2 /* tx */
> + GPIO_121 AF2 /* rx */
> + >;
> + MFP_DEFAULT;
> + };
> +
> + uart2_pmx_func2: uart2_pmx_func2 {
> + pinctrl-single,pins = <
> + GPIO_118 AF2 /* CTS */
> + GPIO_119 AF2 /* RTS */
> + >;
> + MFP_PULL_DOWN;
> + };
> +
> + fp_pmx_func1: fp_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_76 AF0
> + GPIO_81 AF0
> + >;
> + MFP_DEFAULT;
> + };
> +
> + /* AP I2C 8 */
> + twsi8_pmx_func1: twsi8_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_47 AF1
> + GPIO_48 AF1
> + >;
> + MFP_DEFAULT;
> + };
> +
> + nfc_pmx_func0: nfc_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_124 AF0
> + GPIO_123 AF0
> + GPIO_115 AF0
> + VCXO_REQ1 AF1
> + >;
> + MFP_LPM_FLOAT;
> + };
> +
> + nfc_pmx_func0_n3_1: nfc_pmx_func0_n3_1 {
> + pinctrl-single,pins = <
> + GPIO_116 AF0
> + GPIO_115 AF0
> + GPIO_60 AF0
> + >;
> + MFP_DEFAULT;
> + };
> +
> + nfc_pmx_func0_n3_2: nfc_pmx_func0_n3_2 {
> + pinctrl-single,pins = <
> + GPIO_107 AF0
> + >;
> + MFP_PULL_DOWN;
> + };
> +
> + goodix_ts_pmx_func0: goodix_ts_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_05 AF0
> + GPIO_06 AF0
> + >;
> + MFP_PULL_DOWN;
> + };
> +
> +
> + /* Not used pin, pull down and set input in lpm */
> + evb_sensor_pmx_func0: evb_sensor_pmx_func0 {
> + pinctrl-single,pins = <
> + GPIO_78 AF0
> + >;
> + MFP_PULL_DOWN;
> + };
> +
> + /* EVB reset pin for mag sensor, GPIO */
> + evb_sensor_pmx_func1: evb_sensor_pmx_func1 {
> + pinctrl-single,pins = <
> + GPIO_80 AF0
> + >;
> + MFP_PULL_UP;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/asr/asr8751c.dtsi b/arch/arm64/boot/dts/asr/asr8751c.dtsi
> new file mode 100644
> index 0000000..c7222eb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/asr/asr8751c.dtsi
> @@ -0,0 +1,460 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dtsi file for ASR8751C
> + * Copyright (c) 2019, ASR Microelectronics(Shanghai) Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/clock/asr8751c-clk.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_C1: cpu-c1 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0000002>;
> + entry-latency-us = <20>;
> + exit-latency-us = <20>;
> + min-residency-us = <100>;
> + };
> +
> + CPU_C2: cpu-c2 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010005>;
> + entry-latency-us = <40>;
> + exit-latency-us = <40>;
> + min-residency-us = <200>;
> + };
> +
> + CLUSTER_MP2: cluster-mp2 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010055>;
> + entry-latency-us = <80>;
> + exit-latency-us = <80>;
> + min-residency-us = <400>;
> + wakeup-latency-us = <40>;
> + };
> +
> + CHIP_D1P: chip-d1p {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x2010355>;
> + entry-latency-us = <200>;
> + exit-latency-us = <200>;
> + min-residency-us = <1000>;
> + wakeup-latency-us = <80>;
> + };
> +
> + CHIP_D1: chip-d1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x2010455>;
> + entry-latency-us = <300>;
> + exit-latency-us = <300>;
> + min-residency-us = <1200>;
> + wakeup-latency-us = <160>;
> + };
> +
> + CHIP_D2: chip-d2 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x2010555>;
> + entry-latency-us = <400>;
> + exit-latency-us = <400>;
> + min-residency-us = <1500>;
> + wakeup-latency-us = <200>;
> + };
> + };
> +
> + clst0_core_opp_table: opp_table0 {
Use '-' rather than '_':
opp-table0
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp624000000 {
> + opp-hz = /bits/ 64 <624000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <200000>;
> + };
> + opp832000000 {
> + opp-hz = /bits/ 64 <832000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <200000>;
> + };
> + opp1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + opp1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + opp1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + opp1600000000 {
> + opp-hz = /bits/ 64 <1600000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> + clst1_core_opp_table: opp_table1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + opp1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + opp1600000000 {
> + opp-hz = /bits/ 64 <1600000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + opp1900000000 {
> + opp-hz = /bits/ 64 <1900000000>;
> + opp-microvolt = <1500000>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> + cpu-map {
> + cluster0: cluster0 {
> + #cooling-cells = <2>; /* min followed by max */
> + dynamic-pwr-coeff = <89>;
> + static-pwr-base-coeff = <1335>;
> + static-pwr-temp-coeff =
> + <2225 27650 (-286) 10>;
> + enable_ipa_vmin_control;
Not documented.
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1: cluster1 {
> + #cooling-cells = <2>;
> + dynamic-pwr-coeff = <115>;
> + static-pwr-base-coeff = <2157>;
> + static-pwr-temp-coeff =
> + <52330 32960 (-603) 13>;
> + enable_ipa_vmin_control;
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + core2 {
> + cpu = <&cpu6>;
> + };
> + core3 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
'arm,armv8' is only valid for s/w models.
> + reg = <0 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
> + clocks = <&soc_clocks ASR_CLK_CLST0>;
> + operating-points-v2 = <&clst0_core_opp_table>;
> + };
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
> + clocks = <&soc_clocks ASR_CLK_CLST0>;
> + operating-points-v2 = <&clst0_core_opp_table>;
> + };
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0 0x2>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
> + clocks = <&soc_clocks ASR_CLK_CLST0>;
> + operating-points-v2 = <&clst0_core_opp_table>;
> + };
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0 0x3>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
> + clocks = <&soc_clocks ASR_CLK_CLST0>;
> + operating-points-v2 = <&clst0_core_opp_table>;
> + };
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
> + clocks = <&soc_clocks ASR_CLK_CLST1>;
> + operating-points-v2 = <&clst1_core_opp_table>;
> + };
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
> + clocks = <&soc_clocks ASR_CLK_CLST1>;
> + operating-points-v2 = <&clst1_core_opp_table>;
> + };
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0 0x102>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
> + clocks = <&soc_clocks ASR_CLK_CLST1>;
> + operating-points-v2 = <&clst1_core_opp_table>;
> + };
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0 0x103>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_C2 &CLUSTER_MP2 &CHIP_D1P &CHIP_D1>;
> + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
> + clocks = <&soc_clocks ASR_CLK_CLST1>;
> + operating-points-v2 = <&clst1_core_opp_table>;
> + };
> +
> + };
> +
> + energy-costs {
None of this node is documented.
> + /* cpu 0 data is magic data without any evidence */
> + CPU_COST_0: core-cost0 {
> + busy-cost-data = <
> + 195 35 /* 624mhz */
> + 260 48 /* 832mhz */
> + 312 64 /* 1000mhz */
> + 390 95 /* 1248mhz */
> + 438 118 /* 1400mhz */
> + 501 149 /* 1600mhz */
> + >;
> + idle-cost-data = <
> + 6
> + 0
> + 0
> + 0
> + 0
> + 0
> + 0
> + >;
> + };
> + CPU_COST_1: core-cost1 {
> + busy-cost-data = <
> + 538 195 /* 1000mhz */
> + 672 292 /* 1248mhz */
> + 862 441 /* 1600mhz */
> + 1024 640 /* 1900mhz */
> +
> + >;
> + idle-cost-data = <
> + 8
> + 0
> + 0
> + 0
> + 0
> + 0
> + 0
> + >;
> + };
> + CLUSTER_COST_0: cluster-cost0 {
> + busy-cost-data = <
> + 195 7 /* 624mhz */
> + 260 10 /* 832mhz */
> + 312 13 /* 1000mhz */
> + 390 22 /* 1248mhz */
> + 438 29 /* 1400mhz */
> + 501 39 /* 1600mhz */
> + >;
> + idle-cost-data = <
> + 40
> + 50
> + 0
> + 0
> + 0
> + 0
> + 0
> + >;
> + };
> + CLUSTER_COST_1: cluster-cost1 {
> + busy-cost-data = <
> + 538 20 /* 1000mhz */
> + 672 33 /* 1248mhz */
> + 862 54 /* 1600mhz */
> + 1024 86 /* 1900mhz */
> + >;
> + idle-cost-data = <
> + 50
> + 60
> + 0
> + 0
> + 0
> + 0
> + 0
> + >;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + cpu_suspend = <0xc4000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
I believe specifying the numbers is deprecated.
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
> + };
> +
> + gic: interrupt-controller@d8000000 {
> + compatible = "arm,gic-v3";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x0 0xd8000000 0x0 0x200000>,
> + <0x0 0xd8100000 0x0 0x200000>;
> + interrupts = <1 9 0x8>;
> + };
> +
> + generic-timer {
> + compatible = "arm,armv8-timer";
> + /* PPI secure/nonsecure IRQ, active low level-sensitive */
> + interrupts = <1 13 0x8>,
> + <1 14 0x8>,
> + <1 11 0x8>,
> + <1 10 0x8>;
> + clock-frequency = <26000000>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
> + ranges;
You can remove this level and move axi and apb up to the root.
> +
> + axi@d4200000 { /* AXI */
> + compatible = "asr,axi-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0 0xd4200000 0 0x00200000>;
> + ranges = <0 0 0 0xffffffff>;
> +
> + }; /* AXI */
> +
> + apb@d4000000 { /* APB */
> + compatible = "asr,apb-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0 0xd4000000 0 0x00200000>;
> + ranges = <0 0 0 0xffffffff>;
> +
> + uart0: uart@d4017000 {
> + compatible = "asr,uart";
> + reg = <0xd4017000 0x1000>;
> + interrupts = <0 32 0x4>;
> + clock-frequency = <13000000>;
> + clocks = <&soc_clocks ASR_CLK_UART0>;
> + };
> +
> + uart1: uart@d4018000 {
> + compatible = "asr,uart";
> + reg = <0xd4018000 0x1000>;
> + interrupts = <0 33 0x4>;
> + clock-frequency = <13000000>;
> + clocks = <&soc_clocks ASR_CLK_UART1>;
> + };
> +
> + uart2: uart@d4017800 {
> + compatible = "asr,uart";
> + reg = <0xd4017800 0x1000>;
> + interrupts = <0 34 0x4>;
> + clock-frequency = <13000000>;
> + clocks = <&soc_clocks ASR_CLK_UART2>;
> + };
> +
> + pmx: pinmux@d401e000 {
> + compatible = "pinconf-single";
> + reg = <0xd401e000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #gpio-range-cells = <3>;
> + ranges;
> +
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <7>;
> +
> + range: gpio-range {
> + #pinctrl-single,gpio-range-cells = <3>;
> + };
> + };
> + }; /* APB */
> + }; /* soc */
> +
> + soc_clocks: clocks@d4050000{
> + compatible = "asr,8751c-clock";
> + reg = <0x0 0xd4050000 0x0 0x209c>,
> + <0x0 0xd4282800 0x0 0x400>,
> + <0x0 0xd4015000 0x0 0x1000>,
> + <0x0 0xd4090000 0x0 0x1000>,
> + <0x0 0xd4282c00 0x0 0x400>,
> + <0x0 0xd8440000 0x0 0x98>,
> + <0x0 0xd4200000 0x0 0x4280>;
> + reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc";
> + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 14+ messages in thread