From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anson Huang Subject: [PATCH V10 1/5] dt-bindings: pwm: Add i.MX TPM PWM binding Date: Tue, 26 Mar 2019 06:52:23 +0000 Message-ID: <1553582817-29519-2-git-send-email-Anson.Huang@nxp.com> References: <1553582817-29519-1-git-send-email-Anson.Huang@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1553582817-29519-1-git-send-email-Anson.Huang@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "thierry.reding@gmail.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "linux@armlinux.org.uk" , "stefan@agner.ch" , "otavio@ossystems.com.br" , Leonard Crestez , "schnitzeltony@gmail.com" , Robin Gong , "linux-pwm@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Cc: dl-linux-imx List-Id: devicetree@vger.kernel.org Add i.MX TPM(Low Power Timer/Pulse Width Modulation Module) PWM binding. Signed-off-by: Anson Huang --- Changes since V9: - update compatible to contain SoC name; - update example; --- .../devicetree/bindings/pwm/imx-tpm-pwm.txt | 22 ++++++++++++++++++= ++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt b/Docume= ntation/devicetree/bindings/pwm/imx-tpm-pwm.txt new file mode 100644 index 0000000..e9cc199 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt @@ -0,0 +1,22 @@ +Freescale i.MX TPM PWM controller + +Required properties: +- compatible : Should be "fsl,imx7ulp-pwm". +- reg: Physical base address and length of the controller's registers. +- #pwm-cells: Should be 3. See pwm.txt in this directory for a description= of the cells format. +- clocks : The clock provided by the SoC to drive the PWM. +- interrupts: The interrupt for the PWM controller. + +Note: The TPM counter and period counter are shared between multiple chann= els, so all channels +should use same period setting. + +Example: + +tpm4: pwm@40250000 { + compatible =3D "fsl,imx7ulp-pwm"; + reg =3D <0x40250000 0x1000>; + assigned-clocks =3D <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents =3D <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks =3D <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells =3D <3>; +}; --=20 2.7.4