From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: thierry.reding@gmail.com, jonathanh@nvidia.com, talho@nvidia.com,
skomatineni@nvidia.com, broonie@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, kyarlagadda@nvidia.com
Cc: ldewangan@nvidia.com, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH V1 07/26] spi: tegra114: flush fifos
Date: Tue, 26 Mar 2019 22:56:28 -0700 [thread overview]
Message-ID: <1553666207-11414-7-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com>
Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO
overflow or underrun errors.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/spi/spi-tegra114.c | 39 ++++++++++++++++++++++++++++++---------
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 0d20fc489134..477828051aba 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -500,22 +500,37 @@ static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
return 0;
}
-static int tegra_spi_start_dma_based_transfer(
- struct tegra_spi_data *tspi, struct spi_transfer *t)
+static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
{
- u32 val;
- unsigned int len;
- int ret = 0;
+ unsigned long timeout = jiffies + HZ;
u32 status;
- /* Make sure that Rx and Tx fifo are empty */
status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
- dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
- (unsigned)status);
- return -EIO;
+ status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
+ tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
+ while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
+ status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
+ if (time_after(jiffies, timeout)) {
+ dev_err(tspi->dev,
+ "timeout waiting for fifo flush\n");
+ return -EIO;
+ }
+
+ udelay(1);
+ }
}
+ return 0;
+}
+
+static int tegra_spi_start_dma_based_transfer(
+ struct tegra_spi_data *tspi, struct spi_transfer *t)
+{
+ u32 val;
+ unsigned int len;
+ int ret = 0;
+
val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
tegra_spi_writel(tspi, val, SPI_DMA_BLK);
@@ -781,6 +796,9 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi,
dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
tspi->def_command1_reg, (unsigned)command1);
+ ret = tegra_spi_flush_fifos(tspi);
+ if (ret < 0)
+ return ret;
if (total_fifo_words > SPI_FIFO_DEPTH)
ret = tegra_spi_start_dma_based_transfer(tspi, t);
else
@@ -878,6 +896,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master,
(tspi->cur_direction & DATA_DIR_RX))
dmaengine_terminate_all(tspi->rx_dma_chan);
ret = -EIO;
+ tegra_spi_flush_fifos(tspi);
reset_control_assert(tspi->rst);
udelay(2);
reset_control_deassert(tspi->rst);
@@ -931,6 +950,7 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
tspi->status_reg);
dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
tspi->command1_reg, tspi->dma_control_reg);
+ tegra_spi_flush_fifos(tspi);
reset_control_assert(tspi->rst);
udelay(2);
reset_control_deassert(tspi->rst);
@@ -1003,6 +1023,7 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
tspi->status_reg);
dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
tspi->command1_reg, tspi->dma_control_reg);
+ tegra_spi_flush_fifos(tspi);
reset_control_assert(tspi->rst);
udelay(2);
reset_control_deassert(tspi->rst);
--
2.7.4
next prev parent reply other threads:[~2019-03-27 5:56 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 5:56 [PATCH V1 01/26] spi: tegra114: fix PIO transfer Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 02/26] spi: tegra114: clear packed bit for unpacked mode Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: clear packed bit for unpacked mode" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 03/26] spi: tegra114: fix for unpacked mode transfers Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: fix for unpacked mode transfers" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 04/26] spi: tegra114: use packed mode for 32 bits per word Sowjanya Komatineni
2019-04-01 7:39 ` Mark Brown
2019-04-01 18:38 ` Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: use packed mode for 32 bits per word" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 05/26] spi: tegra114: use unpacked mode for below 4 byte transfers Sowjanya Komatineni
2019-04-01 8:26 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 06/26] spi: tegra114: terminate dma and reset on transfer timeout Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: terminate dma and reset on transfer timeout" to the spi tree Mark Brown
2019-03-27 5:56 ` Sowjanya Komatineni [this message]
2019-04-01 8:54 ` Applied "spi: tegra114: flush fifos" " Mark Brown
2019-03-27 5:56 ` [PATCH V1 08/26] spi: tegra114: configure dma burst size to fifo trig level Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 09/26] spi: tegra114: dump SPI registers during timeout Sowjanya Komatineni
2019-04-01 7:39 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 10/26] spi: tegra114: avoid reset call in atomic context Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 11/26] spi: tegra114: reset controller on probe Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: reset controller on probe" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 12/26] spi: tegra114: add SPI_LSB_FIRST support Sowjanya Komatineni
2019-04-01 8:54 ` Applied "spi: tegra114: add SPI_LSB_FIRST support" to the spi tree Mark Brown
2019-03-27 5:56 ` [PATCH V1 13/26] spi: tegra114: add dual mode support Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 14/26] spi: tegra114: add 3 wire transfer " Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 15/26] spi: tegra114: set supported bits_per_word Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 16/26] spi: tegra114: set bus number based on id Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 17/26] spi: tegra114: add support for interrupt mask Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 18/26] spi: tegra114: add support for hw based cs Sowjanya Komatineni
2019-04-01 7:48 ` Mark Brown
2019-04-01 18:40 ` Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 19/26] DT bindings: spi: add spi client device properties Sowjanya Komatineni
2019-04-01 7:37 ` Mark Brown
2019-04-01 17:59 ` Sowjanya Komatineni
2019-04-02 4:52 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 20/26] spi: tegra114: add support for tuning HW CS timing Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties Sowjanya Komatineni
2019-03-31 6:42 ` Rob Herring
2019-04-02 20:27 ` Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 22/26] spi: tegra114: add support for tuning clock delay Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 23/26] spi: tegra114: add support for gpio based cs Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default Sowjanya Komatineni
2019-04-01 7:49 ` Mark Brown
2019-04-01 18:07 ` Sowjanya Komatineni
2019-04-02 4:52 ` Mark Brown
2019-03-27 5:56 ` [PATCH V1 25/26] spi: expand mode and mode_bits support Sowjanya Komatineni
2019-03-27 5:56 ` [PATCH V1 26/26] spi: tegra114: add support for LSBYTE_FIRST Sowjanya Komatineni
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