From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anson Huang Subject: [PATCH V6 3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel Date: Tue, 9 Apr 2019 02:43:23 +0000 Message-ID: <1554777487-31075-3-git-send-email-Anson.Huang@nxp.com> References: <1554777487-31075-1-git-send-email-Anson.Huang@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1554777487-31075-1-git-send-email-Anson.Huang@nxp.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "a.zummo@towertech.it" , "alexandre.belloni@bootlin.com" , Aisheng Dong , "ulf.hansson@linaro.org" , "sboyd@kernel.org" , Peng Fan , Daniel Baluta , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-rtc@vger.kernel.org" Cc: dl-linux-imx List-Id: devicetree@vger.kernel.org On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is used for this function, this patch adds support for it. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng --- No changes. --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0cb9398..70ef3db 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -21,6 +21,7 @@ mmc1 = &usdhc2; mmc2 = &usdhc3; serial0 = &adma_lpuart0; + mu1 = &lsio_mu1; }; cpus { @@ -117,7 +118,8 @@ scu { compatible = "fsl,imx-scu"; mbox-names = "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3"; + "rx0", "rx1", "rx2", "rx3", + "gip3"; mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 @@ -125,7 +127,8 @@ &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 - &lsio_mu1 1 3>; + &lsio_mu1 1 3 + &lsio_mu1 3 3>; clk: clock-controller { compatible = "fsl,imx8qxp-clk"; -- 2.7.4