From: CK Hu <ck.hu@mediatek.com>
To: yongqiang.niu@mediatek.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
airlied@linux.ie, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, robh+dt@kernel.org,
linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 07/25] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
Date: Thu, 11 Apr 2019 13:30:16 +0800 [thread overview]
Message-ID: <1554960616.4768.1.camel@mtksdaap41> (raw)
In-Reply-To: <1553667561-25447-8-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Wed, 2019-03-27 at 14:19 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
> rdma only has single output, but no multi output,
> all these rdma->dsi/dpi usecase should move to mtk_ddp_sout_sel
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 90 +++++++++++++++++-----------------
> 1 file changed, 45 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index e4dafe0..5ae13b0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -281,51 +281,6 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD1_MOUT_EN_RDMA1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> - value = RDMA0_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DSI3;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> - value = RDMA1_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI0;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DPI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI1;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI2;
> - } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> - value = RDMA2_SOUT_DSI3;
> } else {
> value = 0;
> }
> @@ -406,6 +361,51 @@ static unsigned int mtk_ddp_sout_sel(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> *addr = DISP_REG_CONFIG_DSI_SEL;
> value = DSI_SEL_IN_RDMA;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + value = RDMA0_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DSI3;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + value = RDMA1_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI0;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DPI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI1;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI2;
> + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> + value = RDMA2_SOUT_DSI3;
> } else {
> value = 0;
> }
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next prev parent reply other threads:[~2019-04-11 5:30 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 6:18 [PATCH v2 00/25] add drm support for MT8183 yongqiang.niu
2019-03-27 6:18 ` [PATCH v2 01/25] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-03-28 3:18 ` CK Hu
2019-03-27 6:18 ` [PATCH v2 02/25] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-03-27 9:39 ` CK Hu
2019-03-31 6:42 ` Rob Herring
[not found] ` <1553667561-25447-1-git-send-email-yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2019-03-27 6:18 ` [PATCH v2 03/25] drm/mediatek: add mutex mod into ddp private data yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-03-28 1:33 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 04/25] drm/mediatek: add mutex sof " yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-03-28 3:02 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 05/25] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-03-28 3:37 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 06/25] drm/mediatek: redefine mtk_ddp_sout_sel yongqiang.niu
2019-04-11 6:09 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 07/25] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-04-11 5:30 ` CK Hu [this message]
2019-03-27 6:19 ` [PATCH v2 08/25] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-04-11 5:57 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 09/25] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-04-11 10:42 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 10/25] drm/mediatek: add commponent OVL0_2L yongqiang.niu
2019-04-11 6:14 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 11/25] drm/mediatek: add component OVL1_2L yongqiang.niu
2019-03-27 6:19 ` [PATCH v2 12/25] drm/mediatek: add component DITHER yongqiang.niu
2019-04-11 6:28 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 13/25] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-04-11 6:48 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 14/25] drm/medaitek: add layer_nr " yongqiang.niu
2019-04-11 10:57 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 15/25] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-04-11 11:01 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 16/25] drm/mediatek: add ddp write register common api yongqiang.niu
2019-04-11 11:15 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 17/25] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-04-16 7:38 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 18/25] drm/mediatek: add RDMA fifo size error handle yongqiang.niu
2019-04-16 8:00 ` CK Hu
2019-04-16 8:37 ` Yongqiang Niu
2019-04-16 11:31 ` YT Shen
2019-03-27 6:19 ` [PATCH v2 19/25] drm/mediatek: add function mtk_ddp_comp_get_type yongqiang.niu
2019-03-27 6:19 ` [PATCH v2 20/25] drm/mediatek: add ovl0/ovl0_2l usecase yongqiang.niu
2019-04-16 8:20 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 21/25] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-04-11 10:33 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 22/25] drm/mediatek: adjust ddp clock control flow yongqiang.niu
2019-04-16 8:24 ` CK Hu
2019-05-28 5:35 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 23/25] drm/mediatek: add vmap support for mediatek drm yongqiang.niu
2019-04-16 8:30 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 24/25] drm/mediatek: respect page offset for PRIME mmap calls yongqiang.niu
2019-04-16 8:33 ` CK Hu
2019-05-28 5:35 ` CK Hu
2019-03-27 6:19 ` [PATCH v2 25/25] drm/mediatek: enable allow_fb_modifiers for mediatek drm yongqiang.niu
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