From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yash Shah Subject: [PATCH 0/2] L2 cache controller support for SiFive FU540 Date: Thu, 25 Apr 2019 11:24:54 +0530 Message-ID: <1556171696-7741-1-git-send-email-yash.shah@sifive.com> Return-path: Sender: linux-kernel-owner@vger.kernel.org To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, palmer@sifive.com Cc: paul.walmsley@sifive.com, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, mark.rutland@arm.com, robh+dt@kernel.org, sachin.ghadi@sifive.com, Yash Shah List-Id: devicetree@vger.kernel.org This patch series adds an L2 cache controller driver with DT documentation for SiFive FU540-C000. These two patches were initially part of the patch series: 'L2 cache controller and EDAC support for SiFive SoCs' https://lkml.org/lkml/2019/4/15/320 In order to merge L2 cache controller driver without any dependency on EDAC, the L2 cache controller patches are re-posted seperately in this series. The patchset is based on Linux 5.1-rc2 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/L2_cache_controller branch of: https://github.com/yashshah7/riscv-linux.git Yash Shah (2): RISC-V: Add DT documentation for SiFive L2 Cache Controller RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 +++++ arch/riscv/mm/Makefile | 1 + arch/riscv/mm/sifive_l2_cache.c | 224 +++++++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt create mode 100644 arch/riscv/mm/sifive_l2_cache.c -- 1.9.1