From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [v2 4/5] drm/mediatek: add frame size control Date: Wed, 8 May 2019 10:59:14 +0800 Message-ID: <1557284354.31731.9.camel@mtksdaap41> References: <20190416060501.76276-1-jitao.shi@mediatek.com> <20190416060501.76276-5-jitao.shi@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190416060501.76276-5-jitao.shi@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jitao Shi Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , stonea168@163.com, dri-devel@lists.freedesktop.org, yingjoe.chen@mediatek.com, Ajay Kumar , Vincent Palatin , cawa.cheng@mediatek.com, Russell King , Thierry Reding , linux-pwm@vger.kernel.org, Sascha Hauer , Pawel Moll , Ian Campbell , Rob Herring , linux-mediatek@lists.infradead.org, Andy Yan , Matthias Brugger , eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org, Rahul Sharma , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Kumar Gala , Sean Paul List-Id: devicetree@vger.kernel.org SGksIEppdGFvOgoKT24gVHVlLCAyMDE5LTA0LTE2IGF0IDE0OjA1ICswODAwLCBKaXRhbyBTaGkg d3JvdGU6Cj4gT3VyIG5ldyBEU0kgY2hpcCBoYXMgZnJhbWUgc2l6ZSBjb250cm9sLgo+IFNvIGFk ZCB0aGUgZHJpdmVyIGRhdGEgdG8gY29udHJvbCBmb3IgZGlmZmVyZW50IGNoaXBzLgo+IAoKUmV2 aWV3ZWQtYnk6IENLIEh1IDxjay5odUBtZWRpYXRlay5jb20+Cgo+IFNpZ25lZC1vZmYtYnk6IEpp dGFvIFNoaSA8aml0YW8uc2hpQG1lZGlhdGVrLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJt L21lZGlhdGVrL210a19kc2kuYyB8IDUgKysrKysKPiAgMSBmaWxlIGNoYW5nZWQsIDUgaW5zZXJ0 aW9ucygrKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2Rz aS5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kc2kuYwo+IGluZGV4IGJlNDI0MDVh MGE3OC4uNDU4YTcwMGNlNzRjIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRl ay9tdGtfZHNpLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vbWVkaWF0ZWsvbXRrX2RzaS5jCj4g QEAgLTc4LDYgKzc4LDcgQEAKPiAgI2RlZmluZSBEU0lfVkJQX05MCQkweDI0Cj4gICNkZWZpbmUg RFNJX1ZGUF9OTAkJMHgyOAo+ICAjZGVmaW5lIERTSV9WQUNUX05MCQkweDJDCj4gKyNkZWZpbmUg RFNJX1NJWkVfQ09OCQkweDM4Cj4gICNkZWZpbmUgRFNJX0hTQV9XQwkJMHg1MAo+ICAjZGVmaW5l IERTSV9IQlBfV0MJCTB4NTQKPiAgI2RlZmluZSBEU0lfSEZQX1dDCQkweDU4Cj4gQEAgLTE2Miw2 ICsxNjMsNyBAQCBzdHJ1Y3QgcGh5Owo+ICBzdHJ1Y3QgbXRrX2RzaV9kcml2ZXJfZGF0YSB7Cj4g IAljb25zdCB1MzIgcmVnX2NtZHFfb2ZmOwo+ICAJYm9vbCBoYXNfc2hhZG93X2N0bDsKPiArCWJv b2wgaGFzX3NpemVfY3RsOwo+ICB9Owo+ICAKPiAgc3RydWN0IG10a19kc2kgewo+IEBAIC00MzAs NiArNDMyLDkgQEAgc3RhdGljIHZvaWQgbXRrX2RzaV9jb25maWdfdmRvX3RpbWluZyhzdHJ1Y3Qg bXRrX2RzaSAqZHNpKQo+ICAJd3JpdGVsKHZtLT52ZnJvbnRfcG9yY2gsIGRzaS0+cmVncyArIERT SV9WRlBfTkwpOwo+ICAJd3JpdGVsKHZtLT52YWN0aXZlLCBkc2ktPnJlZ3MgKyBEU0lfVkFDVF9O TCk7Cj4gIAo+ICsJaWYgKGRzaS0+ZHJpdmVyX2RhdGEtPmhhc19zaXplX2N0bCkKPiArCQl3cml0 ZWwodm0tPnZhY3RpdmUgPDwgMTYgfCB2bS0+aGFjdGl2ZSwgZHNpLT5yZWdzICsgRFNJX1NJWkVf Q09OKTsKPiArCj4gIAlob3Jpem9udGFsX3N5bmNfYWN0aXZlX2J5dGUgPSAodm0tPmhzeW5jX2xl biAqIGRzaV90bXBfYnVmX2JwcCAtIDEwKTsKPiAgCj4gIAlpZiAoZHNpLT5tb2RlX2ZsYWdzICYg TUlQSV9EU0lfTU9ERV9WSURFT19TWU5DX1BVTFNFKQoKCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVs QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWls bWFuL2xpc3RpbmZvL2RyaS1kZXZlbA==