From: <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Yongqiang Niu <yongqiang.niu@mediatek.com>
Subject: [PATCH v3, 06/27] drm/mediatek: add mutex mod into ddp private data
Date: Wed, 5 Jun 2019 19:42:45 +0800 [thread overview]
Message-ID: <1559734986-7379-7-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1559734986-7379-1-git-send-email-yongqiang.niu@mediatek.com>
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
except mutex mod, mutex mod reg,mutex sof reg,
and mutex sof id will be ddp private data
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 53 +++++++++++++++++++++++-----------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 579ce28..ae94d44 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -41,12 +41,12 @@
#define DISP_REG_CONFIG_DSI_SEL 0x050
#define DISP_REG_CONFIG_DPI_SEL 0x064
-#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
-#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
-#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
-#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
-#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
-#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
+#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
+#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
+#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
+#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
@@ -147,12 +147,16 @@ struct mtk_disp_mutex {
bool claimed;
};
+struct mtk_ddp_data {
+ const unsigned int *mutex_mod;
+};
+
struct mtk_ddp {
struct device *dev;
struct clk *clk;
void __iomem *regs;
struct mtk_disp_mutex mutex[10];
- const unsigned int *mutex_mod;
+ const struct mtk_ddp_data *data;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -202,6 +206,18 @@ struct mtk_ddp {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
};
+static const struct mtk_ddp_data mt2701_ddp_driver_data = {
+ .mutex_mod = mt2701_mutex_mod,
+};
+
+static const struct mtk_ddp_data mt2712_ddp_driver_data = {
+ .mutex_mod = mt2712_mutex_mod,
+};
+
+static const struct mtk_ddp_data mt8173_ddp_driver_data = {
+ .mutex_mod = mt8173_mutex_mod,
+};
+
static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
unsigned int *addr)
@@ -464,15 +480,15 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
reg = MUTEX_SOF_DPI1;
break;
default:
- if (ddp->mutex_mod[id] < 32) {
+ if (ddp->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mutex->id);
reg = readl_relaxed(ddp->regs + offset);
- reg |= 1 << ddp->mutex_mod[id];
+ reg |= 1 << ddp->data->mutex_mod[id];
writel_relaxed(reg, ddp->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(ddp->regs + offset);
- reg |= 1 << (ddp->mutex_mod[id] - 32);
+ reg |= 1 << (ddp->data->mutex_mod[id] - 32);
writel_relaxed(reg, ddp->regs + offset);
}
return;
@@ -502,15 +518,15 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
break;
default:
- if (ddp->mutex_mod[id] < 32) {
+ if (ddp->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mutex->id);
reg = readl_relaxed(ddp->regs + offset);
- reg &= ~(1 << ddp->mutex_mod[id]);
+ reg &= ~(1 << ddp->data->mutex_mod[id]);
writel_relaxed(reg, ddp->regs + offset);
} else {
offset = DISP_REG_MUTEX_MOD2(mutex->id);
reg = readl_relaxed(ddp->regs + offset);
- reg &= ~(1 << (ddp->mutex_mod[id] - 32));
+ reg &= ~(1 << (ddp->data->mutex_mod[id] - 32));
writel_relaxed(reg, ddp->regs + offset);
}
break;
@@ -585,7 +601,7 @@ static int mtk_ddp_probe(struct platform_device *pdev)
return PTR_ERR(ddp->regs);
}
- ddp->mutex_mod = of_device_get_match_data(dev);
+ ddp->data = of_device_get_match_data(dev);
platform_set_drvdata(pdev, ddp);
@@ -598,9 +614,12 @@ static int mtk_ddp_remove(struct platform_device *pdev)
}
static const struct of_device_id ddp_driver_dt_match[] = {
- { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
- { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
- { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
+ { .compatible = "mediatek,mt2701-disp-mutex",
+ .data = &mt2701_ddp_driver_data},
+ { .compatible = "mediatek,mt2712-disp-mutex",
+ .data = &mt2712_ddp_driver_data},
+ { .compatible = "mediatek,mt8173-disp-mutex",
+ .data = &mt8173_ddp_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
--
1.8.1.1.dirty
next prev parent reply other threads:[~2019-06-05 11:42 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-05 11:42 [PATCH v3, 00/27] add drm support for MT8183 yongqiang.niu
2019-06-05 11:42 ` [PATCH v3, 01/27] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-06-06 3:47 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 02/27] dt-bindings: mediatek: add ovl_2l description " yongqiang.niu
2019-07-09 1:37 ` Rob Herring
2019-06-05 11:42 ` [PATCH v3, 03/27] dt-bindings: mediatek: add ccorr " yongqiang.niu
2019-07-09 1:37 ` Rob Herring
2019-06-05 11:42 ` [PATCH v3, 04/27] dt-bindings: mediatek: add dither " yongqiang.niu
2019-07-09 1:37 ` Rob Herring
2019-06-05 11:42 ` yongqiang.niu [this message]
2019-06-06 5:42 ` [PATCH v3, 06/27] drm/mediatek: add mutex mod into ddp private data CK Hu
[not found] ` <1559734986-7379-1-git-send-email-yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2019-06-05 11:42 ` [PATCH v3, 05/27] arm64: dts: add display nodes for mt8183 yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-06-05 11:42 ` [PATCH v3, 07/27] drm/mediatek: add mutex mod register offset into ddp private data yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-06-05 11:42 ` [PATCH v3, 08/27] drm/mediatek: add mutex sof " yongqiang.niu
2019-06-06 6:12 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 09/27] drm/mediatek: add mutex sof register offset " yongqiang.niu
2019-06-13 7:45 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 10/27] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-06-14 2:26 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 11/27] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-06-14 3:28 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 12/27] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-06-05 11:42 ` [PATCH v3, 13/27] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-06-14 3:42 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 14/27] drm/mediatek: add commponent OVL_2L0 yongqiang.niu
2019-06-14 3:54 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 15/27] drm/mediatek: add component OVL_2L1 yongqiang.niu
2019-06-14 3:55 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 16/27] drm/mediatek: add component DITHER yongqiang.niu
2019-06-14 4:36 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 17/27] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-06-14 4:59 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 18/27] drm/medaitek: add layer_nr " yongqiang.niu
2019-06-14 5:02 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 19/27] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-06-17 2:01 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 20/27] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-06-14 5:06 ` CK Hu
2019-06-05 11:43 ` [PATCH v3, 21/27] drm/mediatek: add ovl0/ovl_2l0 usecase yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 22/27] drm/mediatek: distinguish ovl and ovl_2l by layer_nr yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 23/27] drm/mediatek: add connection from ovl0 to ovl_2l0 yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 24/27] drm/mediatek: add connection from RDMA0 to COLOR0 yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 25/27] drm/mediatek: add connection from RDMA1 to DSI0 yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 26/27] drm/mediatek: add clock property check before get it yongqiang.niu
2019-06-17 3:06 ` CK Hu
2019-06-05 11:43 ` [PATCH v3, 27/27] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-06-17 3:30 ` CK Hu
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