From: CK Hu <ck.hu@mediatek.com>
To: yongqiang.niu@mediatek.com
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v3, 16/27] drm/mediatek: add component DITHER
Date: Fri, 14 Jun 2019 12:36:39 +0800 [thread overview]
Message-ID: <1560486999.16718.15.camel@mtksdaap41> (raw)
In-Reply-To: <1559734986-7379-17-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add component DITHER
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32 +++++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
> 2 files changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 5a0ec0f..989024d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -47,6 +47,12 @@
> #define CCORR_RELAY_MODE BIT(0)
> #define DISP_CCORR_SIZE 0x0030
>
> +#define DISP_DITHER_EN 0x0000
> +#define DITHER_EN BIT(0)
> +#define DISP_DITHER_CFG 0x0020
> +#define DITHER_RELAY_MODE BIT(0)
> +#define DISP_DITHER_SIZE 0x0030
> +
> #define DISP_GAMMA_EN 0x0000
> #define DISP_GAMMA_CFG 0x0020
> #define DISP_GAMMA_SIZE 0x0030
> @@ -155,6 +161,24 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> }
>
> +static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc)
> +{
> + writel(h << 16 | w, comp->regs + DISP_DITHER_SIZE);
> + writel(DITHER_RELAY_MODE, comp->regs + DISP_DITHER_CFG);
> +}
> +
> +static void mtk_dither_start(struct mtk_ddp_comp *comp)
> +{
> + writel(DITHER_EN, comp->regs + DISP_DITHER_EN);
> +}
> +
> +static void mtk_dither_stop(struct mtk_ddp_comp *comp)
> +{
> + writel_relaxed(0x0, comp->regs + DISP_DITHER_EN);
> +}
> +
> static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc)
> @@ -209,6 +233,12 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> .stop = mtk_ccorr_stop,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_dither = {
> + .config = mtk_dither_config,
> + .start = mtk_dither_start,
> + .stop = mtk_dither_stop,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_gamma = {
> .gamma_set = mtk_gamma_set,
> .config = mtk_gamma_config,
> @@ -234,6 +264,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
> [MTK_DISP_CCORR] = "ccorr",
> [MTK_DISP_AAL] = "aal",
> [MTK_DISP_GAMMA] = "gamma",
> + [MTK_DISP_DITHER] = "dither",
> [MTK_DISP_UFOE] = "ufoe",
> [MTK_DSI] = "dsi",
> [MTK_DPI] = "dpi",
> @@ -256,6 +287,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
> [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
> + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
> [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL },
> [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index d7ef480..158c1e5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_WDMA,
> MTK_DISP_COLOR,
> MTK_DISP_CCORR,
> + MTK_DISP_DITHER,
> MTK_DISP_AAL,
> MTK_DISP_GAMMA,
> MTK_DISP_UFOE,
> @@ -49,6 +50,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> + DDP_COMPONENT_DITHER,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> DDP_COMPONENT_DSI0,
next prev parent reply other threads:[~2019-06-14 4:36 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-05 11:42 [PATCH v3, 00/27] add drm support for MT8183 yongqiang.niu
2019-06-05 11:42 ` [PATCH v3, 01/27] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-06-06 3:47 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 02/27] dt-bindings: mediatek: add ovl_2l description " yongqiang.niu
2019-07-09 1:37 ` Rob Herring
2019-06-05 11:42 ` [PATCH v3, 03/27] dt-bindings: mediatek: add ccorr " yongqiang.niu
2019-07-09 1:37 ` Rob Herring
2019-06-05 11:42 ` [PATCH v3, 04/27] dt-bindings: mediatek: add dither " yongqiang.niu
2019-07-09 1:37 ` Rob Herring
2019-06-05 11:42 ` [PATCH v3, 06/27] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-06-06 5:42 ` CK Hu
[not found] ` <1559734986-7379-1-git-send-email-yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2019-06-05 11:42 ` [PATCH v3, 05/27] arm64: dts: add display nodes for mt8183 yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-06-05 11:42 ` [PATCH v3, 07/27] drm/mediatek: add mutex mod register offset into ddp private data yongqiang.niu-NuS5LvNUpcJWk0Htik3J/w
2019-06-05 11:42 ` [PATCH v3, 08/27] drm/mediatek: add mutex sof " yongqiang.niu
2019-06-06 6:12 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 09/27] drm/mediatek: add mutex sof register offset " yongqiang.niu
2019-06-13 7:45 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 10/27] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-06-14 2:26 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 11/27] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-06-14 3:28 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 12/27] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel yongqiang.niu
2019-06-05 11:42 ` [PATCH v3, 13/27] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-06-14 3:42 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 14/27] drm/mediatek: add commponent OVL_2L0 yongqiang.niu
2019-06-14 3:54 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 15/27] drm/mediatek: add component OVL_2L1 yongqiang.niu
2019-06-14 3:55 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 16/27] drm/mediatek: add component DITHER yongqiang.niu
2019-06-14 4:36 ` CK Hu [this message]
2019-06-05 11:42 ` [PATCH v3, 17/27] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-06-14 4:59 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 18/27] drm/medaitek: add layer_nr " yongqiang.niu
2019-06-14 5:02 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 19/27] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-06-17 2:01 ` CK Hu
2019-06-05 11:42 ` [PATCH v3, 20/27] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-06-14 5:06 ` CK Hu
2019-06-05 11:43 ` [PATCH v3, 21/27] drm/mediatek: add ovl0/ovl_2l0 usecase yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 22/27] drm/mediatek: distinguish ovl and ovl_2l by layer_nr yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 23/27] drm/mediatek: add connection from ovl0 to ovl_2l0 yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 24/27] drm/mediatek: add connection from RDMA0 to COLOR0 yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 25/27] drm/mediatek: add connection from RDMA1 to DSI0 yongqiang.niu
2019-06-05 11:43 ` [PATCH v3, 26/27] drm/mediatek: add clock property check before get it yongqiang.niu
2019-06-17 3:06 ` CK Hu
2019-06-05 11:43 ` [PATCH v3, 27/27] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-06-17 3:30 ` CK Hu
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