From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7E70CA9EB5 for ; Mon, 4 Nov 2019 15:10:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 95181204EC for ; Mon, 4 Nov 2019 15:10:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728144AbfKDPKd (ORCPT ); Mon, 4 Nov 2019 10:10:33 -0500 Received: from esa6.microchip.iphmx.com ([216.71.154.253]:34760 "EHLO esa6.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727861AbfKDPKc (ORCPT ); Mon, 4 Nov 2019 10:10:32 -0500 Received-SPF: Pass (esa6.microchip.iphmx.com: domain of Claudiu.Beznea@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa6.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="Claudiu.Beznea@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa6.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa6.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa6.microchip.iphmx.com; dkim=none (message not signed) header.i=none; spf=Pass smtp.mailfrom=Claudiu.Beznea@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: motKTvZ+6Oeotl2ub+SwMIOxykHo2/2L6mJaamr7kdhUB8YoCBbnY0qS2eazAe5wcJAYKNQhQ+ qglpJd2H8RTAaDD0GUzpLDYV0yk17Hm7OM5ivzkj3acNVL8IQms73Emot+GHRARwb6SPxkbsyY 88xPY3cLpZ1PkUyLDYL+5o4GysG0bxukuHrCiZHsTtPqhSrghXrgEGaZwz87TwFRU4TnPlftSq Kc0ChJ61LxLHtXaOJsu3tuKAycFOzI+7mIpZdxbTUThBopGKOOF6pJD6E9v//45cVbxBIf4nmb dg8= X-IronPort-AV: E=Sophos;i="5.68,267,1569308400"; d="scan'208";a="52785109" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Nov 2019 08:10:32 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 4 Nov 2019 08:10:24 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.85.251) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Mon, 4 Nov 2019 08:10:21 -0700 From: Claudiu Beznea To: , , , , , , CC: , , , Claudiu Beznea , Rob Herring Subject: [PATCH v2 1/2] dt-bindings: arm: atmel: add bindings for PIT64B Date: Mon, 4 Nov 2019 17:10:03 +0200 Message-ID: <1572880204-4514-2-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572880204-4514-1-git-send-email-claudiu.beznea@microchip.com> References: <1572880204-4514-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Type: text/plain Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for PIT64B timer. Cc: Rob Herring Cc: Nicolas Ferre Signed-off-by: Claudiu Beznea --- Hi Rob, Nicolas, You Reviewed-by/Acked-by v1 [1] of this patch but I didn't collect it in this version since I removed the clock-frequency binding in this version. Thank you! Change in v2: - removed clock-frequency binding [1] https://lore.kernel.org/lkml/1552580772-8499-1-git-send-email-claudiu.beznea@microchip.com/ Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 9fbde401a090..e003a553b986 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -10,6 +10,12 @@ PIT Timer required properties: - interrupts: Should contain interrupt for the PIT which is the IRQ line shared across all System Controller members. +PIT64B Timer required properties: +- compatible: Should be "microchip,sam9x60-pit64b" +- reg: Should contain registers location and length +- interrupts: Should contain interrupt for PIT64B timer +- clocks: Should contain the available clock sources for PIT64B timer. + System Timer (ST) required properties: - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length -- 2.7.4