From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1A45C352A4 for ; Sat, 8 Feb 2020 19:11:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7CBC02464E for ; Sat, 8 Feb 2020 19:11:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="xKTsfFiM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727532AbgBHTLd (ORCPT ); Sat, 8 Feb 2020 14:11:33 -0500 Received: from mail25.static.mailgun.info ([104.130.122.25]:59951 "EHLO mail25.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727478AbgBHTLd (ORCPT ); Sat, 8 Feb 2020 14:11:33 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1581189092; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=q8n608gS8326/gyi7HBwdCGeCCYBMuEP1NHevvyQCK8=; b=xKTsfFiM0CcVK1THu+LUIId+QOF88WTWgMtfOqfjRbI6lNqIr0DnCKWdqZkLo2qYFFzgyxfD 5Q1HTRsZLOrGfbeZEtUsL0m/AhBh9hygDYX/E2WstzqkbGVHU8GVhvxkTIpJSZzbi51cOX+k Rbv/rPq+TE6xDHf2+B1BtudLbrI= X-Mailgun-Sending-Ip: 104.130.122.25 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5e3f07e4.7f1e7fc37340-smtp-out-n02; Sat, 08 Feb 2020 19:11:32 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id E10E4C447A0; Sat, 8 Feb 2020 19:11:30 +0000 (UTC) Received: from smasetty-linux.qualcomm.com (blr-c-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id EA688C447A3; Sat, 8 Feb 2020 19:11:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org EA688C447A3 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, jcrouse@codeaurora.org, mka@chromium.org, dianders@chromium.org, Sharat Masetty Subject: [PATCH v5] arm64: dts: qcom: sc7180: Add A618 gpu dt blob Date: Sun, 9 Feb 2020 00:40:59 +0530 Message-Id: <1581189059-14400-2-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1581189059-14400-1-git-send-email-smasetty@codeaurora.org> References: <1581189059-14400-1-git-send-email-smasetty@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the required dt nodes and properties to enabled A618 GPU. Signed-off-by: Sharat Masetty --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f3fcc5c..5cdcbce 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1043,6 +1043,108 @@ }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk"; + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>, <0>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sc7180-gpucc"; reg = <0 0x05090000 0 0x9000>; -- 1.9.1