[PATCH v3 1/6] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC

[Hanks Chen <hanks.chen@mediatek.com>]

From: Andy Teng <andy.teng@mediatek.com>

Add devicetree bindings for MediaTek MT6779 pinctrl driver.

Change-Id: I92586369564948f2628f70421bcd70668f132c4f
Signed-off-by: Andy Teng <andy.teng@mediatek.com>
---
 .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml  |  208 ++++++++++++++++++++
 1 file changed, 208 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
new file mode 100644
index 0000000..ab6ab01
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6779 Pin Controller Device Tree Bindings
+
+maintainers:
+  - Andy Teng <andy.teng@mediatek.com>
+
+description: |
+  The pin controller node should be the child of a syscon node with the
+  required property:
+  - compatible:  "syscon"
+
+properties:
+  compatible:
+    const: mediatek,mt6779-pinctrl
+
+  reg:
+    minItems: 9
+    maxItems: 9
+    description:
+      physical address base for gpio-related control registers.
+
+  reg-names:
+    - $ref: /schemas/types.yaml#/definitions/string-array
+    description:
+      GPIO base register names.
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+    description:
+      Number of cells in GPIO specifier. Since the generic GPIO
+      binding is used, the amount of cells must be specified as 2. See the below
+      mentioned gpio binding representation for description of particular cells.
+
+  gpio-ranges:
+    minItems: 4
+    maxItems: 4
+    description:
+      GPIO valid number range.
+
+  interrupt-controller: true
+
+  interrupts:
+    minItems: 3
+    maxItems: 3
+    description:
+      The interrupt outputs to sysirq.
+
+  "#interrupt-cells":
+    const: 2
+
+  interrupt-parent:
+    minItems: 1
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - gpio-controller
+  - "#gpio-cells"
+  - gpio-ranges
+  - interrupt-controller
+  - interrupts
+  - "#interrupt-cells"
+  - interrupt-parent
+
+patternProperties:
+  '^.*$':
+  type: object
+    description:
+      A pinctrl node should contain at least one subnodes representing the
+      pinctrl groups available on the machine. Each subnode will list the
+      pins it needs, and how they should be configured, with regard to muxer
+      configuration, pullups, drive strength, input enable/disable and input schmitt.
+
+    properties:
+      pinmux:
+        description: |
+          integer array, represents gpio pin number and mux setting.
+          Supported pin number and mux varies for different SoCs, and are defined
+          as macros in boot/dts/<soc>-pinfunc.h directly.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32-array
+
+      bias-disable:
+        type: boolean
+
+      bias-pull-up:
+        oneOf:
+          - type: boolean
+          - $ref: /schemas/types.yaml#/definitions/uint32
+
+      bias-pull-down:
+        oneOf:
+          - type: boolean
+          - $ref: /schemas/types.yaml#/definitions/uint32
+
+      input-enable:
+        type: boolean
+
+      input-disable:
+        type: boolean
+
+      output-low:
+        type: boolean
+
+      output-high:
+        type: boolean
+
+      input-schmitt-enable:
+        type: boolean
+
+      input-schmitt-disable:
+        type: boolean
+
+      mediatek,pull-up-adv:
+        description: |
+          Pull up setings for 2 pull resistors, R0 and R1. User can
+          configure those special pins. Valid arguments are described as below:
+          0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable.
+          1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+          2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+          3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+          - enum: [0, 1, 2, 3]
+
+      mediatek,pull-down-adv:
+        description: |
+          Pull down settings for 2 pull resistors, R0 and R1. User can
+          configure those special pins. Valid arguments are described as below:
+          0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable.
+          1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+          2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+          3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+          - enum: [0, 1, 2, 3]
+
+      drive-strength:
+        description: |
+          Selects the drive strength for the specified pins in mA.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+          - enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+    required:
+      - pinmux
+
+examples:
+  - |
+      #include "mt6779-pinfunc.h"
+
+      pio: pinctrl@10005000 {
+      compatible = "mediatek,mt6779-pinctrl";
+      reg = <0 0x10005000 0 0x1000>,
+            <0 0x11c20000 0 0x1000>,
+            <0 0x11d10000 0 0x1000>,
+            <0 0x11e20000 0 0x1000>,
+            <0 0x11e70000 0 0x1000>,
+            <0 0x11ea0000 0 0x1000>,
+            <0 0x11f20000 0 0x1000>,
+            <0 0x11f30000 0 0x1000>,
+            <0 0x1000b000 0 0x1000>;
+      reg-names = "gpio", "iocfg_rm",
+        "iocfg_br", "iocfg_lm",
+        "iocfg_lb", "iocfg_rt",
+        "iocfg_lt", "iocfg_tl",
+        "eint";
+      gpio-controller;
+      #gpio-cells = <2>;
+      gpio-ranges = <&pio 0 0 210>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+
+      mmc0_pins_default: mmc0default {
+        pins_cmd_dat {
+          pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
+             <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
+             <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
+             <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
+             <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
+             <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
+             <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
+             <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
+             <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
+          input-enable;
+          mediatek,pull-up-adv = <1>;
+        };
+        pins_clk {
+          pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
+          mediatek,pull-down-adv = <2>;
+        };
+        pins_rst {
+          pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
+          mediatek,pull-up-adv = <0>;
+        };
+      };
+    };
+
-- 
1.7.9.5