From: Yongqiang Niu <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
Yongqiang Niu <yongqiang.niu@mediatek.com>
Subject: [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183
Date: Thu, 23 Jul 2020 10:03:16 +0800 [thread overview]
Message-ID: <1595469798-3824-6-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1595469798-3824-1-git-send-email-yongqiang.niu@mediatek.com>
This patch add display nodes for mt8183
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98 ++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 7b781eb..440cf22 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -31,6 +31,11 @@
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
+ ovl0 = &ovl0;
+ ovl_2l0 = &ovl_2l0;
+ ovl_2l1 = &ovl_2l1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
};
cpus {
@@ -707,9 +712,102 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
#clock-cells = <1>;
};
+ ovl0: ovl@14008000 {
+ compatible = "mediatek,mt8183-disp-ovl";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ };
+
+ ovl_2l0: ovl@14009000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ };
+
+ ovl_2l1: ovl@1400a000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+ };
+
+ rdma0: rdma@1400b000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ mediatek,rdma_fifo_size = <5120>;
+ };
+
+ rdma1: rdma@1400c000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ mediatek,rdma_fifo_size = <2048>;
+ };
+
+ color0: color@1400e000 {
+ compatible = "mediatek,mt8183-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@14010000 {
+ compatible = "mediatek,mt8183-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@14011000 {
+ compatible = "mediatek,mt8183-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ dither0: dither@14012000 {
+ compatible = "mediatek,mt8183-disp-dither";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ };
+
+ mutex: mutex@14016000 {
+ compatible = "mediatek,mt8183-disp-mutex";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ };
+
smi_common: smi@14019000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
reg = <0 0x14019000 0 0x1000>;
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-07-23 2:05 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-23 2:03 [v7, PATCH 0/7] add drm support for MT8183 Yongqiang Niu
2020-07-23 2:03 ` [v7, PATCH 1/7] drm/mediatek: move ddp component defint into mtk_mmsys.h Yongqiang Niu
2020-07-23 9:34 ` Enric Balletbo Serra
2020-07-23 10:04 ` Yongqiang Niu
2020-07-23 16:21 ` Chun-Kuang Hu
2020-07-23 2:03 ` [v7, PATCH 2/7] mtk-mmsys: add mmsys private data Yongqiang Niu
2020-07-23 9:32 ` Enric Balletbo Serra
2020-07-25 3:27 ` Yongqiang Niu
2020-07-28 10:25 ` Enric Balletbo Serra
2020-07-25 2:11 ` Chun-Kuang Hu
2020-07-25 3:13 ` Yongqiang Niu
2020-07-23 2:03 ` [v7, PATCH 3/7] mtk-mmsys: add mt8183 mmsys support Yongqiang Niu
2020-07-24 13:49 ` Nicolas Boichat
2020-07-23 2:03 ` [v7, PATCH 4/7] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display Yongqiang Niu
2020-07-23 15:41 ` Matthias Brugger
2020-07-23 16:59 ` Rob Herring
2020-07-23 2:03 ` Yongqiang Niu [this message]
2020-07-23 15:42 ` [v7, PATCH 5/7] arm64: dts: add display nodes for mt8183 Matthias Brugger
2020-07-23 2:03 ` [v7, PATCH 6/7] drm/mediatek: add fifo_size into rdma private data Yongqiang Niu
2020-07-25 3:50 ` Chun-Kuang Hu
2020-07-23 2:03 ` [v7, PATCH 7/7] drm/mediatek: add support for mediatek SOC MT8183 Yongqiang Niu
2020-07-23 15:40 ` Matthias Brugger
2020-07-25 3:31 ` Yongqiang Niu
2020-07-24 23:24 ` Chun-Kuang Hu
2020-07-25 3:30 ` Yongqiang Niu
2020-07-25 3:45 ` Chun-Kuang Hu
2020-07-27 7:52 ` Yongqiang Niu
2020-07-27 14:50 ` Chun-Kuang Hu
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