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From: Crystal Guo <crystal.guo@mediatek.com>
To: <p.zabel@pengutronix.de>, <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <srv_heupstream@mediatek.com>,
	<linux-mediatek@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<seiya.wang@mediatek.com>, Crystal Guo <crystal.guo@mediatek.com>
Subject: [PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface
Date: Wed, 29 Jul 2020 15:39:16 +0800	[thread overview]
Message-ID: <1596008357-11213-2-git-send-email-crystal.guo@mediatek.com> (raw)
In-Reply-To: <1596008357-11213-1-git-send-email-crystal.guo@mediatek.com>

Add ti_syscon_reset() to integrate assert and deassert together,
and change return value of the reset assert and deassert interface
from regmap_update_bits to regmap_write_bits.

when clear bit is already 1, regmap_update_bits can not write 1 to it again.
Some IC has the feature that, when set bit is 1, the clear bit change
to 1 together. It will truly clear bit to 0 by write 1 to the clear bit

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
 drivers/reset/reset-ti-syscon.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index a2635c2..5a8ec8f 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev,
 	mask = BIT(control->assert_bit);
 	value = (control->flags & ASSERT_SET) ? mask : 0x0;
 
-	return regmap_update_bits(data->regmap, control->assert_offset, mask, value);
+	return regmap_write_bits(data->regmap, control->assert_offset, mask, value);
 }
 
 /**
@@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev,
 	mask = BIT(control->deassert_bit);
 	value = (control->flags & DEASSERT_SET) ? mask : 0x0;
 
-	return regmap_update_bits(data->regmap, control->deassert_offset, mask, value);
+	return regmap_write_bits(data->regmap, control->deassert_offset, mask, value);
 }
 
 /**
@@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev,
 		!(control->flags & STATUS_SET);
 }
 
+static int ti_syscon_reset(struct reset_controller_dev *rcdev,
+			   unsigned long id)
+{
+	ti_syscon_reset_assert(rcdev, id);
+
+	return ti_syscon_reset_deassert(rcdev, id);
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
 	.assert		= ti_syscon_reset_assert,
 	.deassert	= ti_syscon_reset_deassert,
 	.status		= ti_syscon_reset_status,
+	.reset		= ti_syscon_reset,
 };
 
 static int ti_syscon_reset_probe(struct platform_device *pdev)
-- 
1.8.1.1.dirty

  reply	other threads:[~2020-07-29  7:39 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-29  7:39 [PATCH 0/2] adjust the reset assert and deassert interface Crystal Guo
2020-07-29  7:39 ` Crystal Guo [this message]
2020-07-29  7:48   ` [PATCH 1/2] reset-controller: ti: " Matthias Brugger
2020-07-29  8:02     ` Philipp Zabel
2020-07-30  6:27       ` Crystal Guo
2020-07-29  7:39 ` [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node Crystal Guo
2020-07-29  7:45   ` Matthias Brugger
2020-07-29  8:18     ` Crystal Guo

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