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From: Crystal Guo <crystal.guo@mediatek.com>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: "Matthias Brugger" <matthias.bgg@gmail.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	srv_heupstream <srv_heupstream@mediatek.com>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"Seiya Wang (王迺君)" <seiya.wang@mediatek.com>,
	yingjoe.chen@mediatek.com, fan.chen@mediatek.com,
	stanley.chu@mediatek.com
Subject: Re: [PATCH 1/2] reset-controller: ti: adjust the reset assert and deassert interface
Date: Thu, 30 Jul 2020 14:27:21 +0800	[thread overview]
Message-ID: <1596090441.11360.27.camel@mhfsdcap03> (raw)
In-Reply-To: <d259a74ca9e425f9b39ebbf47b0decb6be0beed5.camel@pengutronix.de>

On Wed, 2020-07-29 at 16:02 +0800, Philipp Zabel wrote:
> Hi Crystal, Matthias,
> 
> On Wed, 2020-07-29 at 09:48 +0200, Matthias Brugger wrote:
> > 
> > On 29/07/2020 09:39, Crystal Guo wrote:
> > > Add ti_syscon_reset() to integrate assert and deassert together,
> > > and change return value of the reset assert and deassert interface
> > > from regmap_update_bits to regmap_write_bits.
> > > 
> > > when clear bit is already 1, regmap_update_bits can not write 1 to it again.
> > > Some IC has the feature that, when set bit is 1, the clear bit change
> > > to 1 together. It will truly clear bit to 0 by write 1 to the clear bit
> > > 
> > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> > > ---
> > >   drivers/reset/reset-ti-syscon.c | 13 +++++++++++--
> > >   1 file changed, 11 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
> > > index a2635c2..5a8ec8f 100644
> > > --- a/drivers/reset/reset-ti-syscon.c
> > > +++ b/drivers/reset/reset-ti-syscon.c
> > > @@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev,
> > >   	mask = BIT(control->assert_bit);
> > >   	value = (control->flags & ASSERT_SET) ? mask : 0x0;
> > >   
> > > -	return regmap_update_bits(data->regmap, control->assert_offset, mask, value);
> > > +	return regmap_write_bits(data->regmap, control->assert_offset, mask, value);
> > 
> > Nack, this will break the driver for the other devices.
> 
> I don't think this will break the driver for existing hardware.
> regmap_write_bits() is the same as regmap_update_bits(), it just forces
> the write in case the read already happens to return the correct value.
> Of course it would be good to check that this actually works.

Yes, regmap_write_bits() is the same as regmap_update_bits(), it would
not affect existed users. Or should I use a property to separate
regmap_write_bits() and regmap_update_bits() ?

> 
> > The kernel has to work not just for your SoC but for all devices of all 
> > architectures. You can't just hack something up, that will work on your specific 
> > SoC.
> > 
> > Regards,
> > Matthias 
> > 

This TI driver was intend to be a generic reset controller
(https://lore.kernel.org/patchwork/cover/683585/), so this patch may
not just work on a specific SoC.

Thanks,
Crystal

> > >   }
> > >   
> > >   /**
> > > @@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev,
> > >   	mask = BIT(control->deassert_bit);
> > >   	value = (control->flags & DEASSERT_SET) ? mask : 0x0;
> > >   
> > > -	return regmap_update_bits(data->regmap, control->deassert_offset, mask, value);
> > > +	return regmap_write_bits(data->regmap, control->deassert_offset, mask, value);
> > >   }
> > >   
> > >   /**
> > > @@ -158,10 +158,19 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev,
> > >   		!(control->flags & STATUS_SET);
> > >   }
> > >   
> > > +static int ti_syscon_reset(struct reset_controller_dev *rcdev,
> > > +			   unsigned long id)
> > > +{
> > > +	ti_syscon_reset_assert(rcdev, id);
> > > +
> > > +	return ti_syscon_reset_deassert(rcdev, id);
> > > +}
> > > +
> 
> I'm unsure about this one, though. This is an incompatible change. At
> the very least this would have to be optional depending on compatible.
> 
> regards
> Philipp

I will add a property to make this change be optional, thanks for you
advice.

Thanks,
Crystal



  reply	other threads:[~2020-07-30  6:27 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-29  7:39 [PATCH 0/2] adjust the reset assert and deassert interface Crystal Guo
2020-07-29  7:39 ` [PATCH 1/2] reset-controller: ti: " Crystal Guo
2020-07-29  7:48   ` Matthias Brugger
2020-07-29  8:02     ` Philipp Zabel
2020-07-30  6:27       ` Crystal Guo [this message]
2020-07-29  7:39 ` [PATCH 2/2] arm64: dts: mt8192: add infracfg_rst node Crystal Guo
2020-07-29  7:45   ` Matthias Brugger
2020-07-29  8:18     ` Crystal Guo

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