From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>,
<yamonkar@cadence.com>, <tomi.valkeinen@ti.com>, <jsarha@ti.com>,
<nsekhar@ti.com>
Subject: [PATCH v1 10/13] phy: cadence-torrent: Add single link SGMII/QSGMII register sequences
Date: Fri, 7 Aug 2020 13:46:04 +0200 [thread overview]
Message-ID: <1596800767-784-11-git-send-email-sjakhade@cadence.com> (raw)
In-Reply-To: <1596800767-784-1-git-send-email-sjakhade@cadence.com>
Add support for single link SGMII/QSGMII configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
drivers/phy/cadence/phy-cadence-torrent.c | 89 +++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 216b25512a08..b291b63afba8 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -1824,6 +1824,13 @@ static int cdns_torrent_phy_init(struct phy *phy)
if (phy_type == TYPE_DP)
return cdns_torrent_dp_init(phy);
+ /**
+ * Spread spectrum generation is not required or supported
+ * for SGMII/QSGMII
+ */
+ if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
+ ssc = NO_SSC;
+
/* PHY configuration specific registers for single link */
link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
if (link_cmn_vals) {
@@ -2543,6 +2550,28 @@ static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
.num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
};
+/* Single SGMII/QSGMII link configuration */
+static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
+ {0x0000, PHY_PLL_CFG},
+ {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
+};
+
+static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
+ {0x0000, XCVR_DIAG_HSCLK_SEL},
+ {0x0003, XCVR_DIAG_HSCLK_DIV},
+ {0x0013, XCVR_DIAG_PLLDRC_CTRL}
+};
+
+static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
+ .reg_pairs = sl_sgmii_link_cmn_regs,
+ .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
+};
+
+static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
+ .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
+ .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
+};
+
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
{0x0004, CMN_PLL0_DSM_DIAG_M0},
@@ -2701,6 +2730,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2708,6 +2740,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2734,6 +2769,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2741,6 +2779,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2767,6 +2808,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
@@ -2774,6 +2818,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
@@ -2800,6 +2847,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
@@ -2807,6 +2857,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
@@ -2833,6 +2886,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
@@ -2840,6 +2896,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
@@ -2871,6 +2930,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2878,6 +2940,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2904,6 +2969,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2911,6 +2979,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2937,6 +3008,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
@@ -2944,6 +3018,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
@@ -2970,6 +3047,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
@@ -2977,6 +3057,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
@@ -3003,6 +3086,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
@@ -3010,6 +3096,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
--
2.26.1
next prev parent reply other threads:[~2020-08-07 11:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-07 11:45 [PATCH v1 00/13] PHY: Add support for multilink configurations in Cadence Torrent PHY driver Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 01/13] phy: cadence-torrent: Add single link PCIe support Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 02/13] phy: cadence-torrent: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 03/13] phy: cadence-torrent: Add PHY APB reset support Swapnil Jakhade
2020-08-07 11:45 ` [PATCH v1 04/13] dt-bindings: phy: Add PHY_TYPE_QSGMII definition Swapnil Jakhade
2020-08-17 22:14 ` Rob Herring
2020-08-07 11:45 ` [PATCH v1 05/13] phy: cadence-torrent: Add support for PHY multilink configuration Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 06/13] phy: cadence-torrent: Update PHY reset for " Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 07/13] phy: cadence-torrent: Add clk changes " Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 08/13] phy: cadence-torrent: Add PHY link configuration sequences for single link Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 09/13] phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals Swapnil Jakhade
2020-08-07 11:46 ` Swapnil Jakhade [this message]
2020-08-07 11:46 ` [PATCH v1 11/13] phy: cadence-torrent: Add single link USB register sequences Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 12/13] phy: cadence-torrent: Add PCIe + USB multilink configuration Swapnil Jakhade
2020-08-07 11:46 ` [PATCH v1 13/13] phy: cadence-torrent: Add USB + SGMII/QSGMII " Swapnil Jakhade
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