From: Jacky Bai <ping.bai@nxp.com>
To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de
Cc: festevam@gmail.com, kernel@pengutronix.de, linux-imx@nxp.com,
devicetree@vger.kernel.org
Subject: [PATCH v2 3/3] arm64: dts: imx8mm: Add imx8mm ddr4 evk board support
Date: Mon, 24 Aug 2020 15:20:27 +0800 [thread overview]
Message-ID: <1598253627-25797-3-git-send-email-ping.bai@nxp.com> (raw)
In-Reply-To: <1598253627-25797-1-git-send-email-ping.bai@nxp.com>
Add the board dts support for i.MX8MM DDR4 EVK board.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
Changes for v2: remove the ddrc opp table for now; remove the unnecessary
suffix for gpmi pinctrl node.
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx8mm-ddr4-evk.dts | 57 +++++++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a39f0a1723e0..417c552480f2 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
new file mode 100644
index 000000000000..6c079c0a3a48
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm-evk.dtsi"
+
+/ {
+ model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board";
+ compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";
+
+ leds {
+ pinctrl-0 = <&pinctrl_gpio_led_2>;
+
+ status {
+ gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ nand-on-flash-bbt;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_gpmi_nand: gpmi-nand {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
+ MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
+ MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096
+ MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
+ MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
+ MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
+ MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
+ MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
+ MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
+ MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
+ MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
+ MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
+ MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
+ MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
+ MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
+ MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
+ >;
+ };
+
+ pinctrl_gpio_led_2: gpioled2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
+ >;
+ };
+};
--
2.26.2
prev parent reply other threads:[~2020-08-24 7:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-24 7:20 [PATCH v2 1/3] dt-bindings: arm: fsl: Add imx8mm ddr4 evk board Jacky Bai
2020-08-24 7:20 ` [PATCH v2 2/3] arm64: dts: imx8mm: Split the imx8mm evk board dts to a common dtsi Jacky Bai
2020-08-30 13:44 ` Shawn Guo
2020-08-31 1:19 ` Jacky Bai
2020-08-24 7:20 ` Jacky Bai [this message]
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