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Wed, 2 Sep 2020 00:05:58 -0700 Received: from [10.140.6.6] (helo=xhdappanad40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kDMqD-0002Ee-OK; Wed, 02 Sep 2020 00:05:58 -0700 From: Piyush Mehta To: axboe@kernel.dk, p.zabel@pengutronix.de, robh+dt@kernel.org Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, git@xilinx.com, sgoud@xilinx.com, michal.simek@xilinx.com, Piyush Mehta Subject: [PATCH 1/2] ata: ahci: ceva: Update the driver to support xilinx GT phy Date: Wed, 2 Sep 2020 12:35:47 +0530 Message-Id: <1599030348-3334-2-git-send-email-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599030348-3334-1-git-send-email-piyush.mehta@xilinx.com> References: <1599030348-3334-1-git-send-email-piyush.mehta@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 72391fd3-543c-4c99-e4f5-08d84f0eaa7b X-MS-TrafficTypeDiagnostic: DM5PR02MB2715: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zX0ssyYTIh+YpByftGemdnSnfic/GAzjBjHnpwIlqey7dOBSQsv1pclKG2Ui7iKXZGddsxysLCS8eX9ja0MUdc/XajcJvaUnyZpPXNPwvDubG+UNRI7PmktPCwdGGcrnOp85lt5SdBlgMQWZjF37sYApBvR5u/lsLbsQedFiQp6AEWQ1H/m3YhfeJzXL/4LXMjV9l/aVQwn5+xBaUAlf/TYwlrKERG7+dnODXalXSFFKhCxDeNpZ02vQyKxIZyfBi5/blTwOuS/Pp7MfxHcuyg0EQDDjuDLTVg0rUloP2FO/ApcKxDATxOdIwLDN9dj/4k2r+mrZ1Adn3eWOMqckx0X0nhBsj8LaFoWsuagbOUC9cB5/xBUaxxHaHCzHHy8K8UZYHd6ed7Ewajno17MrXQ== X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapsmtpgw01;PTR:unknown-60-83.xilinx.com;CAT:NONE;SFS:(376002)(136003)(39860400002)(396003)(346002)(46966005)(70206006)(107886003)(316002)(2906002)(8936002)(5660300002)(336012)(8676002)(70586007)(44832011)(6666004)(4326008)(2616005)(82740400003)(9786002)(478600001)(26005)(426003)(36756003)(47076004)(7696005)(83380400001)(15650500001)(82310400003)(186003)(81166007)(356005);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2020 07:06:08.1227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72391fd3-543c-4c99-e4f5-08d84f0eaa7b X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT037.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR02MB2715 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SATA controller used in Xilinx ZynqMP platform uses xilinx GT phy which has 4 GT lanes and can used by 4 peripherals at a time. SATA controller uses 1 GT phy lane among the 4 GT lanes. To configure the GT lane for SATA controller, the below sequence is expected. 1. Assert the SATA controller reset. 2. Configure the xilinx GT phy lane for SATA controller (phy_init). 3. De-assert the SATA controller reset. 4. Wait for PLL of the GT lane used by SATA to be locked (phy_power_on). The ahci_platform_enable_resources() by default does the phy_init() and phy_power_on() but the default sequence doesn't work with Xilinx platforms. Because of this reason, updated the driver to support the new sequence. Signed-off-by: Piyush Mehta --- drivers/ata/ahci_ceva.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index b10fd4c..5341d89 100644 --- a/drivers/ata/ahci_ceva.c +++ b/drivers/ata/ahci_ceva.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "ahci.h" /* Vendor Specific Register Offsets */ @@ -87,6 +88,7 @@ struct ceva_ahci_priv { u32 axicc; bool is_cci_enabled; int flags; + struct reset_control *rst; }; static unsigned int ceva_ahci_read_id(struct ata_device *dev, @@ -194,7 +196,7 @@ static int ceva_ahci_probe(struct platform_device *pdev) struct ahci_host_priv *hpriv; struct ceva_ahci_priv *cevapriv; enum dev_dma_attr attr; - int rc; + int rc, i; cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL); if (!cevapriv) @@ -202,14 +204,42 @@ static int ceva_ahci_probe(struct platform_device *pdev) cevapriv->ahci_pdev = pdev; + cevapriv->rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(cevapriv->rst)) { + if (PTR_ERR(cevapriv->rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to get reset: %ld\n", + PTR_ERR(cevapriv->rst)); + return PTR_ERR(cevapriv->rst); + } + hpriv = ahci_platform_get_resources(pdev, 0); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); - rc = ahci_platform_enable_resources(hpriv); + rc = ahci_platform_enable_clks(hpriv); if (rc) return rc; + /* Assert the controller reset */ + reset_control_assert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_init(hpriv->phys[i]); + if (rc) + return rc; + } + + /* De-assert the controller reset */ + reset_control_deassert(cevapriv->rst); + + for (i = 0; i < hpriv->nports; i++) { + rc = phy_power_on(hpriv->phys[i]); + if (rc) { + phy_exit(hpriv->phys[i]); + return rc; + } + } + if (of_property_read_bool(np, "ceva,broken-gen2")) cevapriv->flags = CEVA_FLAG_BROKEN_GEN2; -- 2.7.4