From: Crystal Guo <crystal.guo@mediatek.com>
To: Suman Anna <s-anna@ti.com>
Cc: "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
srv_heupstream <srv_heupstream@mediatek.com>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"Seiya Wang (王迺君)" <seiya.wang@mediatek.com>,
"Stanley Chu (朱原陞)" <stanley.chu@mediatek.com>,
"Yingjoe Chen (陳英洲)" <Yingjoe.Chen@mediatek.com>,
"Fan Chen (陳凡)" <fan.chen@mediatek.com>,
"Yong Liang (梁勇)" <Yong.Liang@mediatek.com>
Subject: Re: [v4,4/4] arm64: dts: mt8192: add infracfg_rst node
Date: Tue, 8 Sep 2020 21:26:58 +0800 [thread overview]
Message-ID: <1599571618.14806.7.camel@mhfsdcap03> (raw)
In-Reply-To: <211bd78f-3b70-1e65-eea9-75cc73a3dfdd@ti.com>
On Thu, 2020-09-03 at 07:29 +0800, Suman Anna wrote:
> Hi Crystal,
>
> On 8/16/20 10:03 PM, Crystal Guo wrote:
> > add infracfg_rst node which is for MT8192 platform
> >
> > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
>
> I understand you are posting these together for complete reference, but driver
> subsystem maintainers typically don't pick dts patches. In anycase, can you
> clarify if your registers are self-clearing registers?
>
> regards
> Suman
>
Hi Suman,
Thanks for your reply.
Our reset registers are not self-clearing, it needs to set the clear bit
to 1 to clear the related bit.
And should I separate this dts patch from the patch sets?
regards
Crystal
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 931e1ca17220..a0cb9904706b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -10,6 +10,7 @@
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > #include <dt-bindings/power/mt8192-power.h>
> > +#include <dt-bindings/reset/ti-syscon.h>
> >
> > / {
> > compatible = "mediatek,mt8192";
> > @@ -219,9 +220,17 @@
> > };
> >
> > infracfg: infracfg@10001000 {
> > - compatible = "mediatek,mt8192-infracfg", "syscon";
> > + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> > reg = <0 0x10001000 0 0x1000>;
> > #clock-cells = <1>;
> > +
> > + infracfg_rst: reset-controller {
> > + compatible = "mediatek,infra-reset", "ti,syscon-reset";
> > + #reset-cells = <1>;
> > + ti,reset-bits = <
> > + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: pcie */
> > + >;
> > + };
> > };
> >
> > pericfg: pericfg@10003000 {
> >
>
next prev parent reply other threads:[~2020-09-08 15:00 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-17 3:03 [v4,0/4] introduce TI reset controller for MT8192 SoC Crystal Guo
2020-08-17 3:03 ` [v4,1/4] dt-binding: reset-controller: ti: add reset-duration-us property Crystal Guo
2020-08-25 17:42 ` Rob Herring
2020-08-26 11:09 ` Crystal Guo
2020-08-17 3:03 ` [v4,2/4] dt-binding: reset-controller: ti: add 'mediatek,infra-reset' to compatible Crystal Guo
2020-08-25 19:02 ` Rob Herring
2020-08-26 11:09 ` Crystal Guo
2020-09-02 23:25 ` Suman Anna
2020-09-08 18:49 ` Rob Herring
2020-09-09 15:10 ` Suman Anna
2020-09-09 18:20 ` Rob Herring
2020-08-17 3:03 ` [v4,3/4] reset-controller: ti: introduce a new reset handler Crystal Guo
2020-09-02 23:40 ` Suman Anna
2020-09-09 2:57 ` Crystal Guo
2020-09-09 15:39 ` Suman Anna
2020-09-11 2:42 ` Crystal Guo
2020-09-11 2:52 ` Suman Anna
2020-09-11 6:07 ` Crystal Guo
2020-09-11 14:26 ` Philipp Zabel
2020-09-11 14:44 ` Suman Anna
2020-09-14 14:00 ` Crystal Guo
2020-09-29 13:54 ` Crystal Guo
2020-08-17 3:03 ` [v4,4/4] arm64: dts: mt8192: add infracfg_rst node Crystal Guo
2020-09-02 23:29 ` Suman Anna
2020-09-08 13:26 ` Crystal Guo [this message]
2020-09-08 15:51 ` Suman Anna
[not found] ` <5065a23627a34212aa62df646dbf00ee@mtkmbs05n1.mediatek.inc>
2020-09-02 3:03 ` [v4,0/4] introduce TI reset controller for MT8192 SoC Crystal Guo
-- strict thread matches above, loose matches on Subject: below --
2020-08-17 2:48 [v3,0/6] " Crystal Guo
2020-08-17 2:48 ` [v4,4/4] arm64: dts: mt8192: add infracfg_rst node Crystal Guo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1599571618.14806.7.camel@mhfsdcap03 \
--to=crystal.guo@mediatek.com \
--cc=Yingjoe.Chen@mediatek.com \
--cc=Yong.Liang@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=fan.chen@mediatek.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=s-anna@ti.com \
--cc=seiya.wang@mediatek.com \
--cc=srv_heupstream@mediatek.com \
--cc=stanley.chu@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).