Re: [PATCH net-next 1/5] dt-bindings: net: r8a779f0-ether-switch: Add ACLK

[Andrew Lunn <andrew@lunn.ch>]

On Mon, May 29, 2023 at 07:36:03PM +0100, Conor Dooley wrote:
> Hey,
> 
> On Mon, May 29, 2023 at 05:08:36PM +0900, Yoshihiro Shimoda wrote:
> > Add ACLK of GWCA which needs to calculate registers' values for
> > rate limiter feature.
> > 
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> >  .../bindings/net/renesas,r8a779f0-ether-switch.yaml    | 10 ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml b/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml
> > index e933a1e48d67..cbe05fdcadaf 100644
> > --- a/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml
> > +++ b/Documentation/devicetree/bindings/net/renesas,r8a779f0-ether-switch.yaml
> > @@ -75,7 +75,12 @@ properties:
> >        - const: rmac2_phy
> >  
> >    clocks:
> > -    maxItems: 1
> > +    maxItems: 2
> > +
> > +  clock-names:
> > +    items:
> > +      - const: fck
> > +      - const: aclk
> 
> Since having both clocks is now required, please add some detail in the
> commit message about why that is the case. Reading it sounds like this
> is an optional new feature & not something that is required.

This is something i wondered about, backwards compatibility with old
DT blobs. In the C code it is optional, and has a default clock rate
if the clock is not present. So the yaml should not enforce an aclk
member.

	Andrew