From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>,
<yamonkar@cadence.com>, <tomi.valkeinen@ti.com>, <jsarha@ti.com>,
<nsekhar@ti.com>
Subject: [PATCH v3 09/13] phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals
Date: Thu, 17 Sep 2020 09:30:42 +0200 [thread overview]
Message-ID: <1600327846-9733-10-git-send-email-sjakhade@cadence.com> (raw)
In-Reply-To: <1600327846-9733-1-git-send-email-sjakhade@cadence.com>
Include PHY_PLL_CFG as a first register value to configure in
link_cmn_vals array values.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
drivers/phy/cadence/phy-cadence-torrent.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 0367c0fe15e2..0c4abe959f19 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -1830,7 +1830,14 @@ static int cdns_torrent_phy_init(struct phy *phy)
reg_pairs = link_cmn_vals->reg_pairs;
num_regs = link_cmn_vals->num_regs;
regmap = cdns_phy->regmap_common_cdb;
- for (i = 0; i < num_regs; i++)
+
+ /**
+ * First array value in link_cmn_vals must be of
+ * PHY_PLL_CFG register
+ */
+ regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
+
+ for (i = 1; i < num_regs; i++)
regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
}
@@ -1907,8 +1914,6 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
phy_t1 = cdns_phy->phys[0].phy_type;
phy_t2 = cdns_phy->phys[1].phy_type;
- regmap_field_write(cdns_phy->phy_pll_cfg, 0x0003);
-
/**
* First configure the PHY for first link with phy_t1. Get the array
* values as [phy_t1][phy_t2][ssc].
@@ -1944,7 +1949,15 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
reg_pairs = link_cmn_vals->reg_pairs;
num_regs = link_cmn_vals->num_regs;
regmap = cdns_phy->regmap_common_cdb;
- for (i = 0; i < num_regs; i++)
+
+ /**
+ * First array value in link_cmn_vals must be of
+ * PHY_PLL_CFG register
+ */
+ regmap_field_write(cdns_phy->phy_pll_cfg,
+ reg_pairs[0].val);
+
+ for (i = 1; i < num_regs; i++)
regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
}
@@ -2280,6 +2293,7 @@ static int cdns_torrent_phy_remove(struct platform_device *pdev)
/* PCIe and SGMII/QSGMII Unique SSC link configuration */
static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
+ {0x0003, PHY_PLL_CFG},
{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
{0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
--
2.26.1
next prev parent reply other threads:[~2020-09-17 8:20 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-17 7:30 [PATCH v3 00/13] PHY: Add support for multilink configurations in Cadence Torrent PHY driver Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 01/13] phy: cadence-torrent: Add single link PCIe support Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 02/13] phy: cadence-torrent: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 03/13] phy: cadence-torrent: Add PHY APB reset support Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 04/13] dt-bindings: phy: Add PHY_TYPE_QSGMII definition Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 05/13] phy: cadence-torrent: Add support for PHY multilink configuration Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 06/13] phy: cadence-torrent: Update PHY reset for " Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 07/13] phy: cadence-torrent: Add clk changes " Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 08/13] phy: cadence-torrent: Add PHY link configuration sequences for single link Swapnil Jakhade
2020-09-17 7:30 ` Swapnil Jakhade [this message]
2020-09-17 7:30 ` [PATCH v3 10/13] phy: cadence-torrent: Add single link SGMII/QSGMII register sequences Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 11/13] phy: cadence-torrent: Add single link USB " Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 12/13] phy: cadence-torrent: Add PCIe + USB multilink configuration Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 13/13] phy: cadence-torrent: Add USB + SGMII/QSGMII " Swapnil Jakhade
2020-09-18 5:17 ` [PATCH v3 00/13] PHY: Add support for multilink configurations in Cadence Torrent PHY driver Vinod Koul
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