From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>,
<yamonkar@cadence.com>, <tomi.valkeinen@ti.com>, <jsarha@ti.com>,
<nsekhar@ti.com>
Subject: [PATCH v3 10/13] phy: cadence-torrent: Add single link SGMII/QSGMII register sequences
Date: Thu, 17 Sep 2020 09:30:43 +0200 [thread overview]
Message-ID: <1600327846-9733-11-git-send-email-sjakhade@cadence.com> (raw)
In-Reply-To: <1600327846-9733-1-git-send-email-sjakhade@cadence.com>
Add support for single link SGMII/QSGMII configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
drivers/phy/cadence/phy-cadence-torrent.c | 89 +++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 0c4abe959f19..844ec0ee8c66 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -1824,6 +1824,13 @@ static int cdns_torrent_phy_init(struct phy *phy)
if (phy_type == TYPE_DP)
return cdns_torrent_dp_init(phy);
+ /**
+ * Spread spectrum generation is not required or supported
+ * for SGMII/QSGMII
+ */
+ if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
+ ssc = NO_SSC;
+
/* PHY configuration specific registers for single link */
link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
if (link_cmn_vals) {
@@ -2540,6 +2547,28 @@ static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
.num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
};
+/* Single SGMII/QSGMII link configuration */
+static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
+ {0x0000, PHY_PLL_CFG},
+ {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
+};
+
+static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
+ {0x0000, XCVR_DIAG_HSCLK_SEL},
+ {0x0003, XCVR_DIAG_HSCLK_DIV},
+ {0x0013, XCVR_DIAG_PLLDRC_CTRL}
+};
+
+static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
+ .reg_pairs = sl_sgmii_link_cmn_regs,
+ .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
+};
+
+static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
+ .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
+ .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
+};
+
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
{0x0004, CMN_PLL0_DSM_DIAG_M0},
@@ -2698,6 +2727,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2705,6 +2737,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2731,6 +2766,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2738,6 +2776,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2764,6 +2805,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
@@ -2771,6 +2815,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
@@ -2797,6 +2844,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
@@ -2804,6 +2854,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
@@ -2830,6 +2883,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
@@ -2837,6 +2893,9 @@ static const struct cdns_torrent_data cdns_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
@@ -2868,6 +2927,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2875,6 +2937,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_link_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &pcie_sgmii_link_cmn_vals,
[EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
@@ -2901,6 +2966,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2908,6 +2976,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
[EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
@@ -2934,6 +3005,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
@@ -2941,6 +3015,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
@@ -2967,6 +3044,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
@@ -2974,6 +3054,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
@@ -3000,6 +3083,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_SGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
@@ -3007,6 +3093,9 @@ static const struct cdns_torrent_data ti_j721e_map_torrent = {
},
},
[TYPE_QSGMII] = {
+ [TYPE_NONE] = {
+ [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
+ },
[TYPE_PCIE] = {
[NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
[EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
--
2.26.1
next prev parent reply other threads:[~2020-09-17 8:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-17 7:30 [PATCH v3 00/13] PHY: Add support for multilink configurations in Cadence Torrent PHY driver Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 01/13] phy: cadence-torrent: Add single link PCIe support Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 02/13] phy: cadence-torrent: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 03/13] phy: cadence-torrent: Add PHY APB reset support Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 04/13] dt-bindings: phy: Add PHY_TYPE_QSGMII definition Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 05/13] phy: cadence-torrent: Add support for PHY multilink configuration Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 06/13] phy: cadence-torrent: Update PHY reset for " Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 07/13] phy: cadence-torrent: Add clk changes " Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 08/13] phy: cadence-torrent: Add PHY link configuration sequences for single link Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 09/13] phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals Swapnil Jakhade
2020-09-17 7:30 ` Swapnil Jakhade [this message]
2020-09-17 7:30 ` [PATCH v3 11/13] phy: cadence-torrent: Add single link USB register sequences Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 12/13] phy: cadence-torrent: Add PCIe + USB multilink configuration Swapnil Jakhade
2020-09-17 7:30 ` [PATCH v3 13/13] phy: cadence-torrent: Add USB + SGMII/QSGMII " Swapnil Jakhade
2020-09-18 5:17 ` [PATCH v3 00/13] PHY: Add support for multilink configurations in Cadence Torrent PHY driver Vinod Koul
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1600327846-9733-11-git-send-email-sjakhade@cadence.com \
--to=sjakhade@cadence.com \
--cc=devicetree@vger.kernel.org \
--cc=jsarha@ti.com \
--cc=kishon@ti.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mparab@cadence.com \
--cc=nsekhar@ti.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=tomi.valkeinen@ti.com \
--cc=vkoul@kernel.org \
--cc=yamonkar@cadence.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).