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Svyatoslav Ryhel Cc: Thierry Reding , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Jonas =?UTF-8?B?U2Nod8O2YmVs?= , Charan Pedumuru , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v2 16/23] staging: media: tegra-video: tegra20: simplify format align calculations Date: Wed, 24 Sep 2025 13:47:13 +0900 Message-ID: <16036554.JCcGWNJJiE@senjougahara> In-Reply-To: References: <20250906135345.241229-1-clamor95@gmail.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-ClientProxiedBy: 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SA0PR12MB7478 On Tuesday, September 23, 2025 3:50=E2=80=AFPM Svyatoslav Ryhel wrote: > =D0=B2=D1=82, 23 =D0=B2=D0=B5=D1=80. 2025=E2=80=AF=D1=80. =D0=BE 09:11 Sv= yatoslav Ryhel =D0=BF=D0=B8=D1=88=D0=B5: > > > > =D0=B2=D1=82, 23 =D0=B2=D0=B5=D1=80. 2025=E2=80=AF=D1=80. =D0=BE 09:04 = Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > > > > > On Monday, September 22, 2025 4:36=E2=80=AFPM Svyatoslav Ryhel wrote: > > > > =D0=BF=D0=BD, 22 =D0=B2=D0=B5=D1=80. 2025=E2=80=AF=D1=80. =D0=BE 10= :27 Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > > > > > > > > > On Monday, September 22, 2025 3:30=E2=80=AFPM Svyatoslav Ryhel wr= ote: > > > > > > =D0=BF=D0=BD, 22 =D0=B2=D0=B5=D1=80. 2025=E2=80=AF=D1=80. =D0= =BE 09:23 Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > > > > > > > > > > > > > On Monday, September 22, 2025 2:13=E2=80=AFPM Svyatoslav Ryhe= l wrote: > > > > > > > > =D0=BF=D0=BD, 22 =D0=B2=D0=B5=D1=80. 2025=E2=80=AF=D1=80. = =D0=BE 07:44 Mikko Perttunen =D0=BF=D0=B8=D1=88=D0= =B5: > > > > > > > > > > > > > > > > > > On Saturday, September 6, 2025 10:53=E2=80=AFPM Svyatosla= v Ryhel wrote: > > > > > > > > > > Simplify format align calculations by slightly modifyin= g supported formats > > > > > > > > > > structure. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Svyatoslav Ryhel > > > > > > > > > > --- > > > > > > > > > > drivers/staging/media/tegra-video/tegra20.c | 41 +++++= +++------------- > > > > > > > > > > 1 file changed, 16 insertions(+), 25 deletions(-) > > > > > > > > > > > > > > > > > > > > diff --git a/drivers/staging/media/tegra-video/tegra20.= c b/drivers/staging/media/tegra-video/tegra20.c > > > > > > > > > > index 6e0b3b728623..781c4e8ec856 100644 > > > > > > > > > > --- a/drivers/staging/media/tegra-video/tegra20.c > > > > > > > > > > +++ b/drivers/staging/media/tegra-video/tegra20.c > > > > > > > > > > @@ -280,20 +280,8 @@ static void tegra20_fmt_align(stru= ct v4l2_pix_format *pix, unsigned int bpp) > > > > > > > > > > pix->width =3D clamp(pix->width, TEGRA20_MIN_WI= DTH, TEGRA20_MAX_WIDTH); > > > > > > > > > > pix->height =3D clamp(pix->height, TEGRA20_MIN_HE= IGHT, TEGRA20_MAX_HEIGHT); > > > > > > > > > > > > > > > > > > > > - switch (pix->pixelformat) { > > > > > > > > > > - case V4L2_PIX_FMT_UYVY: > > > > > > > > > > - case V4L2_PIX_FMT_VYUY: > > > > > > > > > > - case V4L2_PIX_FMT_YUYV: > > > > > > > > > > - case V4L2_PIX_FMT_YVYU: > > > > > > > > > > - pix->bytesperline =3D roundup(pix->width,= 2) * 2; > > > > > > > > > > - pix->sizeimage =3D roundup(pix->width, 2)= * 2 * pix->height; > > > > > > > > > > - break; > > > > > > > > > > - case V4L2_PIX_FMT_YUV420: > > > > > > > > > > - case V4L2_PIX_FMT_YVU420: > > > > > > > > > > - pix->bytesperline =3D roundup(pix->width,= 8); > > > > > > > > > > - pix->sizeimage =3D roundup(pix->width, 8)= * pix->height * 3 / 2; > > > > > > > > > > - break; > > > > > > > > > > - } > > > > > > > > > > + pix->bytesperline =3D DIV_ROUND_UP(pix->width * b= pp, 8); > > > > > > > > > > > > > > > > > > Assuming the bpp is coming from the format table below, t= his changes the value of bytesperline for planar formats. With this it'll b= e (width * 12) / 8 i.e. width * 3/2, which doesn't sound right. > > > > > > > > > > > > > > > > > > > > > > > > > Downstream uses soc_mbus_bytes_per_line for this calculatio= n which was > > > > > > > > deprecated some time ago, here is a fragment > > > > > > > > > > > > > > > > s32 soc_mbus_bytes_per_line(u32 width, const struct soc_mbu= s_pixelfmt *mf) > > > > > > > > { > > > > > > > > if (mf->fourcc =3D=3D V4L2_PIX_FMT_JPEG) > > > > > > > > return 0; > > > > > > > > > > > > > > > > if (mf->layout !=3D SOC_MBUS_LAYOUT_PACKED) > > > > > > > > return width * mf->bits_per_sample / 8; > > > > > > > > > > > > > > > > switch (mf->packing) { > > > > > > > > case SOC_MBUS_PACKING_NONE: > > > > > > > > return width * mf->bits_per_sample / 8; > > > > > > > > case SOC_MBUS_PACKING_2X8_PADHI: > > > > > > > > case SOC_MBUS_PACKING_2X8_PADLO: > > > > > > > > case SOC_MBUS_PACKING_EXTEND16: > > > > > > > > return width * 2; > > > > > > > > case SOC_MBUS_PACKING_1_5X8: > > > > > > > > return width * 3 / 2; > > > > > > > > case SOC_MBUS_PACKING_VARIABLE: > > > > > > > > return 0; > > > > > > > > } > > > > > > > > return -EINVAL; > > > > > > > > } > > > > > > > > > > > > > > > > V4L2_PIX_FMT_YUV420 and V4L2_PIX_FMT_YVU420 are classified = as > > > > > > > > SOC_MBUS_PACKING_1_5X8 hence we get width * 3/2 > > > > > > > > > > > > > > Googling this brings up the entry > > > > > > > > > > > > > > { > > > > > > > .code =3D V4L2_MBUS_FMT_YUYV8_1_5X8, > > > > > > > .fmt =3D { > > > > > > > .fourcc =3D V4L2_PIX_FMT_YUV4= 20, > > > > > > > .name =3D "YUYV 4:2:0", > > > > > > > .bits_per_sample =3D 8, > > > > > > > .packing =3D SOC_MBUS_= PACKING_1_5X8, > > > > > > > .order =3D SOC_MBUS_ORDER_LE= , > > > > > > > .layout =3D SOC_MBUS_LAYOUT_P= ACKED, > > > > > > > }, > > > > > > > } > > > > > > > > > > > > > > which matches that you're describing. It doesn't make sense t= o me, since it at the same time specifies PIX_FMT_YUV420 (which is planar w= ith 3 planes, as documented by include/uapi/linux/videodev2.h), and LAYOUT_= PACKED > > > > > > > > > > > > > > /** > > > > > > > * enum soc_mbus_layout - planes layout in memory > > > > > > > * @SOC_MBUS_LAYOUT_PACKED: color components pack= ed > > > > > > > * @SOC_MBUS_LAYOUT_PLANAR_2Y_U_V: YUV components stored= in 3 planes (4:2:2) > > > > > > > * @SOC_MBUS_LAYOUT_PLANAR_2Y_C: YUV components stored= in a luma and a > > > > > > > * chroma plane (C plane= is half the size > > > > > > > * of Y plane) > > > > > > > * @SOC_MBUS_LAYOUT_PLANAR_Y_C: YUV components stored= in a luma and a > > > > > > > * chroma plane (C plane= is the same size > > > > > > > * as Y plane) > > > > > > > */ > > > > > > > enum soc_mbus_layout { > > > > > > > SOC_MBUS_LAYOUT_PACKED =3D 0, > > > > > > > SOC_MBUS_LAYOUT_PLANAR_2Y_U_V, > > > > > > > SOC_MBUS_LAYOUT_PLANAR_2Y_C, > > > > > > > SOC_MBUS_LAYOUT_PLANAR_Y_C, > > > > > > > }; > > > > > > > > > > > > > > i.e. non-planar. The code in the driver is handling it as thr= ee planes as well, with addresses VB0_BASE_ADDRESS/VB0_BASE_ADDRESS_U/VB0_B= ASE_ADDRESS_V. Since the planes are separate, there should be no need to ha= ve more than 'width' samples per line. > > > > > > > > > > > > > > > > > > > I did not invent this, I have just simplified this calculation = from > > > > > > downstream, output values remain same. I have no cameras which = can > > > > > > output V4L2_PIX_FMT_YUV420 or V4L2_PIX_FMT_YVU420 so I cannot t= est if > > > > > > this works either. Other YUV and RAW formats were tested on rea= l HW > > > > > > and work perfectly fine. > > > > > > > > > > My understanding from the code was, that the MEDIA_BUS_FMT_ forma= ts listed in the video format table refer to the input formats from the cam= era, and the V4L2_PIX_FMT_ formats to output formats from VI. Hence VI coul= d input UYVY8_2X8 and write to memory in YUV420. The code dealing with V4L2= _PIX_FMT_ values seems to be related to the output to memory. Is it possibl= e to test this (your camera -> VI converts to YUV420) or am I mistaken? > > > > > > > > > > > > > Camera I am testing with has no YUV420 options available and from w= hat > > > > I can tell there is no way to force VI to output in YUV420 unless > > > > camera supports it. Any format manipulations should requite hooking= up > > > > ISP, or am I missing smth? > > > > > > From a quick look at the spec it looks to me like for YUV422 packed i= nput formats specifically, VI should be able to convert to YUV420. If that = were not the case, e.g. 'TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YUV= 420),' would not make sense anyway as it's talking about both YUV422 packed= input data and then also YUV420. > > > > > > > After additional checking you are correct, VI should be able to > > perform YUV442 to YUV440. One of the reasons why VI is not exposing > > YUV440 may be video-centric nature of the driver, so that it exposes > > only formats supported by camera and VI. I will double check which > > formats video device exposes. What should I test exactly? > > If you are able to test, I would like to see the following (with YUV422 inp= ut camera, VI set to output YUV420) (1) Output image is correct (2) Check output image bytes per line (e.g. with a hex editor) (3) If output image bytes per line is 3/2 * width, try changing it to 1 * w= idth and repeating test >=20 > Alternatively, since code that I propose matches in output with one > that was before, changes can be applied and revised once there will be > such need. Especially, since YUV422 and RAW8/10 work fine and were > tested. I am not sure there will be many use cases which deliberately > target YUV420. >=20 Yeah, since it's a pre-existing issue, that makes sense. However, I'd still= add a comment to the bytes per line calculation with a reference to the do= wnstream code it's based on, and that it produces an unexpected 3/2 * width= for YUV420. Mikko > > > > > > > > > It's certainly possible that the current code is functional -- if= bytesperline is set to a too large value and that information flows to use= rspace, it could still read the buffer. It would just waste memory. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > + pix->sizeimage =3D pix->bytesperline * pix->heigh= t; > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > /* > > > > > > > > > > @@ -576,20 +564,23 @@ static const struct tegra_vi_ops = tegra20_vi_ops =3D { > > > > > > > > > > .vi_stop_streaming =3D tegra20_vi_stop_streaming, > > > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > -#define TEGRA20_VIDEO_FMT(MBUS_CODE, BPP, FOURCC) \ > > > > > > > > > > -{ \ > > > > > > > > > > - .code =3D MEDIA_BUS_FMT_##MBUS_CODE, = \ > > > > > > > > > > - .bpp =3D BPP, = \ > > > > > > > > > > - .fourcc =3D V4L2_PIX_FMT_##FOURCC, = \ > > > > > > > > > > +#define TEGRA20_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_C= ODE, BPP, FOURCC) \ > > > > > > > > > > +{ = \ > > > > > > > > > > + .img_dt =3D TEGRA_IMAGE_DT_##DATA_TYPE, = \ > > > > > > > > > > + .bit_width =3D BIT_WIDTH, = \ > > > > > > > > > > + .code =3D MEDIA_BUS_FMT_##MBUS_CODE, = \ > > > > > > > > > > + .bpp =3D BPP, = \ > > > > > > > > > > + .fourcc =3D V4L2_PIX_FMT_##FOURCC, = \ > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > static const struct tegra_video_format tegra20_video_f= ormats[] =3D { > > > > > > > > > > - TEGRA20_VIDEO_FMT(UYVY8_2X8, 2, UYVY), > > > > > > > > > > - TEGRA20_VIDEO_FMT(VYUY8_2X8, 2, VYUY), > > > > > > > > > > - TEGRA20_VIDEO_FMT(YUYV8_2X8, 2, YUYV), > > > > > > > > > > - TEGRA20_VIDEO_FMT(YVYU8_2X8, 2, YVYU), > > > > > > > > > > - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YUV420), > > > > > > > > > > - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YVU420), > > > > > > > > > > + /* YUV422 */ > > > > > > > > > > + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 16, UY= VY), > > > > > > > > > > + TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 16, VY= UY), > > > > > > > > > > + TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 16, YU= YV), > > > > > > > > > > + TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 16, YV= YU), > > > > > > > > > > + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YU= V420), > > > > > > > > > > + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YV= U420), > > > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > const struct tegra_vi_soc tegra20_vi_soc =3D { > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >