From: Yash Shah <yash.shah@sifive.com>
To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com
Cc: aou@eecs.berkeley.edu, Jonathan.Cameron@huawei.com,
wsa@kernel.org, sam@ravnborg.org, sagar.kadam@sifive.com,
anup@brainfault.org, bp@suse.de, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
sachin.ghadi@sifive.com, Yash Shah <yash.shah@sifive.com>
Subject: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740
Date: Thu, 12 Nov 2020 14:41:13 +0530 [thread overview]
Message-ID: <1605172274-44916-1-git-send-email-yash.shah@sifive.com> (raw)
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++-----
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index efc0198..4873d5c 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -27,6 +27,7 @@ select:
items:
- enum:
- sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache
required:
- compatible
@@ -34,7 +35,9 @@ select:
properties:
compatible:
items:
- - const: sifive,fu540-c000-ccache
+ - enum:
+ - sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache
- const: cache
cache-block-size:
@@ -51,12 +54,6 @@ properties:
cache-unified: true
- interrupts:
- description: |
- Must contain entries for DirError, DataError and DataFail signals.
- minItems: 3
- maxItems: 3
-
reg:
maxItems: 1
@@ -67,6 +64,28 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
+if:
+ properties:
+ compatible:
+ contains:
+ const: sifive,fu540-c000-ccache
+
+then:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DataError and DataFail signals.
+ minItems: 3
+ maxItems: 3
+
+else:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DirFail, DataError, DataFail signals.
+ minItems: 4
+ maxItems: 4
+
additionalProperties: false
required:
--
2.7.4
next reply other threads:[~2020-11-12 9:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-12 9:11 Yash Shah [this message]
2020-11-12 9:11 ` [PATCH 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740 Yash Shah
2020-11-21 12:54 ` [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add support for " Rob Herring
2020-11-23 10:32 ` Yash Shah
2020-11-30 15:36 ` Rob Herring
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