From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8894BC4361B for ; Sat, 5 Dec 2020 15:12:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 506922312B for ; Sat, 5 Dec 2020 15:12:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726366AbgLEPLk (ORCPT ); Sat, 5 Dec 2020 10:11:40 -0500 Received: from mail.kernel.org ([198.145.29.99]:44138 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726873AbgLEO73 (ORCPT ); Sat, 5 Dec 2020 09:59:29 -0500 From: Krzysztof Kozlowski Authentication-Results: mail.kernel.org; dkim=permerror (bad message/signature format) To: Dmitry Osipenko , Mikko Perttunen , Nicolas Chauvet , Georgi Djakov , Peter Geis , MyungJoo Ham , Viresh Kumar , Thierry Reding , Michael Turquette , Kyungmin Park , Stephen Boyd , Rob Herring , Jonathan Hunter , Peter De Schrijver , Chanwoo Choi Cc: Krzysztof Kozlowski , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: Re: [PATCH v11 00/10] Introduce memory interconnect for NVIDIA Tegra SoCs Date: Sat, 5 Dec 2020 15:09:11 +0100 Message-Id: <160717730565.9414.18193998919736710677.b4-ty@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201203192439.16177-1-digetx@gmail.com> References: <20201203192439.16177-1-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 3 Dec 2020 22:24:29 +0300, Dmitry Osipenko wrote: > This series brings initial support for memory interconnect to Tegra20, > Tegra30 and Tegra124 SoCs. > > For the starter only display controllers and devfreq devices are getting > interconnect API support, others could be supported later on. The display > controllers have the biggest demand for interconnect API right now because > dynamic memory frequency scaling can't be done safely without taking into > account bandwidth requirement from the displays. In particular this series > fixes distorted display output on T30 Ouya and T124 TK1 devices. > > [...] Applied, thanks! [01/10] dt-bindings: memory: tegra20: emc: Document opp-supported-hw property [02/10] memory: tegra20: Support hardware versioning and clean up OPP table initialization [03/10] memory: tegra30: Support interconnect framework commit: 01a51facb74fb337ff9fe734caa85dd6e246ef48 Best regards, -- Krzysztof Kozlowski