From: Heiko Stuebner <heiko@sntech.de>
To: Matthias Kaehlcke <mka@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Douglas Anderson <dianders@chromium.org>
Subject: Re: [PATCH] ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron
Date: Thu, 11 Apr 2019 13:36:41 +0200 [thread overview]
Message-ID: <1607560.o8nNNBouYe@phil> (raw)
In-Reply-To: <20190410183010.21307-1-mka@chromium.org>
Am Mittwoch, 10. April 2019, 20:30:10 CEST schrieb Matthias Kaehlcke:
> Some veyron devices have a Bluetooth controller connected on UART0.
> The UART needs to operate at a high speed, however setting the clock
> rate at initialization has no practical effect. During initialization
> user space adjusts the UART baudrate multiple times, which ends up
> changing the SCLK rate. After a successful initiatalization the clk
> is running at the desired speed (48MHz).
>
> Remove the unnecessary clock rate configuration from the DT.
>
> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
applied for 5.2 with Doug's RB.
Thanks
Heiko
prev parent reply other threads:[~2019-04-11 11:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 18:30 [PATCH] ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron Matthias Kaehlcke
[not found] ` <20190410183010.21307-1-mka-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2019-04-10 23:53 ` Doug Anderson
2019-04-11 11:36 ` Heiko Stuebner [this message]
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